On chip weighted random patterns

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 344-352

  Savir, Jacob ^a  

^a University Heights   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED WEIGHT PATTERN TEST APPROACH;

CODES (SYMBOLS); FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; SHIFT REGISTERS;

INTEGRATED CIRCUIT TESTING;

EID: 0031362433     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

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