Ultra-shallow junction formation by spike annealing in a lamp-based or hot-walled rapid thermal annealing system: Effect of ramp-up rate

Materials Science in Semiconductor Processing

Volumn 1, Issue 3-4, 1998, Pages 237-241

  Agarwal, Aditya ^a   Fiory, Anthony T ^b   Gossmann, Hans Joachim L ^b   Rafferty, Conor S ^b   Frisella, Peter ^a  

^a EATON CORPORATION   (United States)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001652427     PISSN: 13698001     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1369-8001(98)00030-4     Document Type: Article

References (10)

1. National technology roadmap for semiconductors. San Jose: Semiconductor Industry Association, 1997.
2. Giles MD. J Electrochem Soc 1991;138:138.
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4. Gossmann H.-J. In: Huff, H.R., Goselle, U., Tsuya, H., editors. Semiconductor silicon. ECS Proc. 98(1), 1998. p. 884.
5. Fair RB, Tsai JCC. J Electrochem Soc 1977;124:1107.
6. Agarwal A, Gossmann H-J, Eaglesham DJ, Pelaz L, Herner SB, Jacobson DC et al. IEDM Tech Digest 1997;0:367.
7. Agarwal A, Gossmann H-J, Eaglesham DJ, Pelaz L, Jacobson DC, Haynes TE et al. Appl Phys Lett 1997;71:3141.
8. Shishiguchi S, Mineji A, Hayashi T, Saito S. VLSI Tech Symp 1997;1059.
9. Agarwal A., Fiory A.T., Gossmann H.-J., Rafferty C.S., Frisella P., Hebb J., Jackson J., Appl Phys Lett, submitted for publication.
10. Saito S. Paper presented at MRS Spring 1998 Meeting, San Francisco.