Generalized Reed-Muller expressions: Complexity and an exact minimization algorithm

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E79-A, Issue 12, 1996, Pages 2123-2130

  Sasao, Tsutomu ^a   Debnath, Debatosh ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

AND EXOR; Binary decision diagrams; Complexity of logic networks; Easily testable networks; Logic minimization; Reed Muller expression

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; DECISION TABLES; EQUIVALENCE CLASSES; LOGIC CIRCUITS;

BINARY DECISION DIAGRAMS; GENERALIZED REED-MULLER EXPRESSION; LOGIC MINIMIZATION;

LOGIC DESIGN;

EID: 0030391634     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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