Derivation of a logarithmic time carry lookahead addition circuit

Journal of Functional Programming

Volumn 14, Issue 6, 2004, Pages 697-713

  O'Donnell, John T ^a   Rünger, Gudula ^b  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH DEPTH; DIGITAL CIRCUIT DESCRIPTION LANGUAGE; FORMAL EQUATIONAL REASONING; SEQUENTIAL ADDER;

ADDERS; ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; DATA REDUCTION; INTEGER PROGRAMMING; LOGIC GATES; STORAGE ALLOCATION (COMPUTER); THEOREM PROVING;

DIGITAL CIRCUITS;

EID: 9744263271     PISSN: 09567968     EISSN: None     Source Type: Journal    
DOI: 10.1017/S0956796804005180     Document Type: Article

References (10)

1. Cormen, T., Leiserson, C. and Rivest, R., (1990) Introduction to Algorithms. MIT Press.
2. Fisher, A. L. and Ghuloum, A. M. (1994) Parallelizing complex scans and reductions. Conference on Programming Language Design and Implementation, pp. 135-146. ACM.
3. Guibas, L. and Vuillemin, J. (1982) On fast binary addition in nMOS technologies. Proc. of IEEE Conference, ICCC, pp. 147-151.
4. Harrison, P. G. (1991) Towards the synthesis of static parallel algorithms: a categorical approach. Proc. Working Conf. on Constructing Programs from Specifications. IFIP.
5. Karp, R. M. and Ramachandran, F. (1990) Parallel Algorithms for Shared-Memory Machines. In: van Leeuwen, J. (editor), Handbook of theoretical computer science: Vol. A: Algorithms and Complexity, pp. 869-941. MIT Press/Elsevier.
6. Ladner, R. and Fischer, M. (1980) Parallel prefix computation. J. ACM, 4(October).
7. Maessen, J.-W. (1994) Eliminating intermediate lists in pH using local transformations. M Eng thesis, Massachusetts Institute of Technology.
8. Mead, C. and Conway, L. (1980) Introduction to VLSI Systems. Addison-Wesley.
9. O'Donnell, J. (1994) A correctness proof of parallel scan. Parallel Process. Lett. 4(3), 329-338.
10. O'Donnell, J. (2002) Overview of Hydra: A concurrent language for synchronous digital circuit design. In: Proceedings 16th International Parallel & Distributed Processing Symposium (IPOPS): Workshop on Parallel and Distribued Scientific and Engineering Computing with Applications - PDSECA, p. 234 and CD. IEEE Computer Society.