Evaluation of substrate noise in CMOS and low-noise logic cells

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 750-753

  Albuquerque, Edgar F M ^a   Silva, Manuel M ^a  

^a INESC   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; COMPLEMENTARY OUTPUT; LOGIC CELLS; LOGIC FAMILIES; RESISTIVE SUBSTRATES; SMALL CELLS; SUBSTRATE NOISE; SUPPLY VOLTAGES;

CELLS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CYTOLOGY; INDUCTANCE; LOGIC DEVICES;

NOISE ABATEMENT;

EID: 8844274978     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922346     Document Type: Conference Paper

References (9)

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3. D. Allstot, G. Liang, H. C. Yang. "Current-steering CMOS logic family", U.S. Patent No. 5162674.
4. E. Albuquerque, and M. Silva, "A New Low-Noise Logic Family for Mixed-Signal ICs", IEEE Trans. Circuits Syst.-I, vol. 46, pp. 1498-1500, Dec. 1999.
5. E. Albuquerque, and M. Silva, "Current-Balanced Logic (CBL) Cells with Complementary Outputs", in Proc. DCIS'99, pp. 791-794, November 1999.
6. A.J. van Genderen, N.P. van der Meijs and T. Smedes. "Fast Computation of Substrate Resistances in Large Circuits", in Proc. ED&TC, pp. 560-565, March 1996.
7. M. Heijningen, et. al., "Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates", IEEE J. Solid-Stale Circuits, vol. 35, pp. 1002-1008, July 2000.
8. SPACE v 4.7.1. HELIOS v 1.4.1 layout to circuit extractor, can be found at website http://cobalt.et.tudelft.nl/-space/.
9. E. Albuquerque, and M. Silva, "A Comparative Study of Low-Noise Logic Cells For Mixed Mode Integrated Circuits", in Proc. IEEE Int. Symp. Circuits Syst. vol. V, pp. 73-76, May 2000.