Accurate modeling of layout parasitic to forecast EMI emitted from a DC-DC converter

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn 1, Issue , 2004, Pages 278-283

  Musznicki, Piotr ^a   Schanen, Jean Luc ^b   Allard, Bruno ^c   Chrzan, Piotr J ^a  

^a GDANSK UNIVERSITY OF TECHNOLOGY   (Poland)

^b LABORATOIRE D ELECTROTECHNIQUE DE GRENOBLE   (France)

^c Univ Claude Bernard Lyon1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DC-DC CONVERTERS; INSULATED METAL SUBSTRATES (IMS); PARASITIC CAPACITANCE; TEMPORAL SIMULATIONS;

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INSULATION; ELECTROMAGNETIC COMPATIBILITY; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; SCHEMATIC DIAGRAMS; SIGNAL INTERFERENCE;

POWER CONVERTERS;

EID: 8744272427     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PESC.2004.1355756     Document Type: Conference Paper

References (11)

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