Integration and performances of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 15-17

  Gosset L G ^a   Chhun, S ^a   Farcy, A ^b   Casanova, N ^b   Arnal, V ^b   Besling, W F A ^a   Torres, J ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COPPER COMPOUNDS; ELECTRIC RESISTANCE; ELECTRODEPOSITION; ETCHING; INTEGRATING CIRCUITS; LEAKAGE CURRENTS; OPTIMIZATION; SURFACE TREATMENT; THICKNESS MEASUREMENT;

INTERCONNECT NETWORK; METALLIC DEPOSITION; SHIELDING ANALYSIS; SIGNAL PROPAGATION;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 8644244765     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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