Impact of dielectrics and metals properties on electrical performances of advanced on-chip interconnects

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 161-163

  Bermond, C ^a   Flechet B ^a   Farcy, A ^b   Arnal, V ^b   Torres, J ^b   Le Carval, G ^c   Angenieux G ^a   Salik, R ^d  

^a UNIVERSITÉ DE SAVOIE   (France)

^b STMICROELECTRONICS   (France)

^c CEA LETI   (France)

^d Cadence   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; LOW-K DIELECTRIC;

COPPER METALLIZATION; COUPLED LINES; ELECTRICAL MODELS; ELECTRICAL PERFORMANCE; METALS PROPERTIES; ON-CHIP INTERCONNECTS; SIMULATION PROCEDURES; ULTRA LOW-K DIELECTRICS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961717902     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014920     Document Type: Conference Paper

References (5)

1. A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections", IEEE Trans. On Microwave Theory and Techniques, vol. 45, No 10, pp. 1836-1846, Oct. 1997.
2. 2 On-Chip Interconnects for High Speed Digital Circuits", Proc. of IITC 2001, San Francisco.
3. K. Yamashita et al., "On-chip Interconnect Evaluation on Delay Time Increase by Crosstalk", Proc. of IEDM 1999, Washington.
4. K. Mosig et al, "Integration of Porous Ultra Low-k Dielectric with CVD Barriers", Proc. of IEDM 2001, Washington D.C.
5. V. Arnal et al., "Integration of a 3 Level Cu - SiO2 Air Gap Interconnect for Sub 0.1 micron CMOS Technologies", Proc. of IITC 2001, San Francisco.