VLSI architecture for multi-resolution three step search algorithm

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 2, Issue , 2003, Pages 918-921

  Sarma, Monalisa ^a   Samanta, Debasis ^a   Dhar, Anindya Sundar ^b  

^a NORTH EASTERN REGIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

ASIC; Block matching motion estimation; Image processing; ITSI architecture; Video compression

Indexed keywords

IMAGE COMPRESSION; MOTION ESTIMATION;

ARCHITECTURE-BASED; CONTROL OVERHEAD; EFFECTIVE SOLUTION; EXISTING ARCHITECTURES; NUMBER OF GATES; REDUCED SWITCHING; THREE-STEP SEARCH; VLSI ARCHITECTURES;

VLSI CIRCUITS;

EID: 85085492863     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277360     Document Type: Conference Paper

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