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Volumn , Issue , 2003, Pages

An all-digital A/D converter for fast conversion with 4-TAD parallel construction using moving-average filtering

Author keywords

ADC; All digital; Moving average

Indexed keywords

DATA HANDLING; DELAY CIRCUITS; DIGITAL FILTERS; LOW PASS FILTERS;

EID: 85084020582     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (11)

References (11)
  • 1
    • 0037248737 scopus 로고    scopus 로고
    • An all-digital analog-to-digital converter with 12-pV/LSB using moving-average filtering
    • Jan
    • T. Watanabe, T. Mizuno, Y. Makino, “An all-digital analog-to-digital converter with 12-pV/LSB using moving-average filtering,” IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 120-125, Jan. 2003.
    • (2003) IEEE Journal of Solid-State Circuits , vol.38 , Issue.1 , pp. 120-125
    • Watanabe, T.1    Mizuno, T.2    Makino, Y.3
  • 2
    • 0036228562 scopus 로고    scopus 로고
    • A 6b 1.6GSample/s flash ADC in 0.18pm CMOS using averaging termination
    • Feb
    • P. Scholtens, M. Vertregt, “A 6b 1.6GSample/s flash ADC in 0.18pm CMOS using averaging termination,” in ISSCC Digest o f Technical Papers, pp. 168-169, Feb. 2002.
    • (2002) ISSCC Digest O F Technical Papers , pp. 168-169
    • Scholtens, P.1    Vertregt, M.2
  • 4
    • 0036231850 scopus 로고    scopus 로고
    • A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration
    • Feb
    • S. M. Jamal, D. Fu, P. J. Hurst, S. H. Lewis, “A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration,” in ISSCC Digest o f Technical Papers, pp. 172-173, Feb. 2002.
    • (2002) ISSCC Digest O F Technical Papers , pp. 172-173
    • Jamal, S.M.1    Fu, D.2    Hurst, P.J.3    Lewis, S.H.4
  • 5
    • 0036227049 scopus 로고    scopus 로고
    • A 16mw 30MSample/s 10b pipelined A/D converter using a pseudo-differential architecture
    • Feb
    • D. Miyazaki, M. Furuta, S. Kawahito, “A 16mW 30MSample/s 10b pipelined A/D converter using a pseudo-differential architecture,” in ISSCC Digest o f Technical Papers, pp. 174-175, Feb. 2002.
    • (2002) ISSCC Digest O F Technical Papers , pp. 174-175
    • Miyazaki, D.1    Furuta, M.2    Kawahito, S.3
  • 6
    • 0029290334 scopus 로고
    • Overview of low-power ULSI circuit techniques
    • April
    • T. Kuroda, T. Sakurai, “Overview of low-power ULSI circuit techniques,” IEICE Trans. Electron., vol. E78-C, no. 4, April 1995, pp. 334-344.
    • (1995) IEICE Trans. Electron. , vol.E78-C , Issue.4 , pp. 334-344
    • Kuroda, T.1    Sakurai, T.2
  • 7
    • 0027814934 scopus 로고
    • A CMOS time-to-digital converter LSI with half-nanosecond resolution using a ring gate delay line
    • Dec
    • T. Watanabe, Y. Makino, Y. Ohtsuka, S. Akita, T. Hattori, “A CMOS time-to-digital converter LSI with half-nanosecond resolution using a ring gate delay line,” IEICE Trans. Electron., vol. E76-C, no. 12, pp. 1774-1779, Dec. 1993.
    • (1993) IEICE Trans. Electron. , vol.E76-C , Issue.12 , pp. 1774-1779
    • Watanabe, T.1    Makino, Y.2    Ohtsuka, Y.3    Akita, S.4    Hattori, T.5
  • 9
    • 0032050259 scopus 로고    scopus 로고
    • Development of a time-to-digital converter IC for laser radar
    • April
    • T. Watanabe, S. Agatsuma, H. Isomura, Y. Ohtsuka, S. Akita, T. Hattori, “Development of a time-to-digital converter IC for laser radar,” JSAE Review, vol. 19, no. 2, pp. 161-165, April 1998.
    • (1998) JSAE Review , vol.19 , Issue.2 , pp. 161-165
    • Watanabe, T.1    Agatsuma, S.2    Isomura, H.3    Ohtsuka, Y.4    Akita, S.5    Hattori, T.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.