On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1997, Pages 246-247

  Cong, Jason ^a   Peck, John ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; C (PROGRAMMING LANGUAGE); COMPUTER HARDWARE; COMPUTER SOFTWARE; COMPUTER WORKSTATIONS; DECODING; INTERFACES (COMPUTER); LOGIC GATES; PARALLEL PROCESSING SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS; HARDWARE ACCELERATOR; LOGIC SYNTHESIS; RECONFIGURABLE COPROCESSOR; TAUTOLOGY CHECKING;

ALGORITHMS;

EID: 0031339617     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)