A process and temperature compensated ring oscillator

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 283-286

  Shyu, Yang Shyung ^a   Wu, Jiin Chuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85047320684     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824084     Document Type: Conference Paper

References (8)

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2. M. G. Johnson, et al., "A variable delay line PLL for CPU-coprocessor synchronization, " IEEE Journal of Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
3. M. P. Flynn, et al., "A 1. 2-um CMOS Current-Controlled Oscillator, " IEEE Journal of Solid-State Circuits, vol. 25, pp. 982-987, Jul. 1992.
4. K. Kato, et al., "A low-power 128-MHz VCO for monolithic PLL IC's, " IEEE Journal of Solid-State Circuits, vol. 23, pp. 160-165, Feb. 1991.
5. I. I. Novof, et al., "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and +-50ps Jitter, " IEEE Journal of Solid-State Circuits, vol. 30, pp. 1259-1266, Nov. 1995.
6. J. G. Maneatis, et al., "Precise Delay Generation Using Coupled Oscillators, " IEEE Journal of Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.
7. J. G. Maneatis, et al., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, " IEEE Journal of Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
8. D. Min, et al., "Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's, " IEEE Journal of Solid-State Circuits, vol. 27, pp. 626-631, Apr. 1992. 3.