Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1996, Pages 277-280

  Gabara, Thaddeus ^a   Fischer, Wilhlem ^a   Harrington, John ^a   Troutman, William ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CIRCUIT OSCILLATIONS; MATHEMATICAL MODELS; RESISTORS; RESONANT CIRCUITS; SWITCHING CIRCUITS; TRANSISTORS;

AUTOMATIC TRANSISTOR SIZING METHOD; GROUND BOUNCE; INTEGRATED RESISTIVE ELEMENT; INTERNAL CAPACITIVE LOAD; PARASITIC RLC CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0029717455     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)