High performance Al dual damascene process with elevated double stoppers

Proceedings of the IEEE 1998 International Interconnect Technology Conference, IITC 1998

Volumn 1998-June, Issue , 1998, Pages 143-145

  Nakamura, N ^a   Anand, M B ^a   Wada, J ^a   Oikawa, Y ^a   Katata, T ^a   Shiba, K ^a   Shibata, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CAPACITANCE; SILICON NITRIDE; WIRE;

DAMASCENE STRUCTURE; DUAL DAMASCENE; DUAL DAMASCENE PROCESS; ELECTRICAL CHARACTERISTIC; INTERCONNECT WIRES; LOW RESISTANCE; SPUTTER PROCESS; WIRE CAPACITANCE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 85039954480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1998.704774     Document Type: Conference Paper

References (6)

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2. C. W. Kaanta S. G. Bombardier, W. J. Cote, W. R. Hil1, GKerszykowski, W. E. Cronin et al, " Dual Damascene: A ULSI Wiring Technology", in Proceedings of 8" International VLSI Multilevel Interconnection Conference, pp. 155-152, June 1991.
3. K. Kikuta T. Nakajima, k. Ueno and T. kikkawa, "Multilevel planarized Trench-Aluminum (PTA) Interconnection using Reflow Sputtering and Chemical Mechanical Polishing", in International Electron Devices Meeting 1993 Technology Digest, pp. 285-288, Dec. 1993.
4. R. V. Joshi, IEEE Electron Device Letters, Vo1. 15, No. 3, march, 1993, pp. 129-132.
5. S. Venkatesan, A. V. Gelatos, V. Misra, R. Islam, J. Cope, Y. Yu et al, "A High Performance 1. 8V,0. 20pm CMOS Technology with Copper Metallization", in International Electron Devices Meeting 1997 Technology Digest, pp. 769-772, Dec. 1997.
6. J. Wada, Y. Oikawa, M. B. Anand, N. Nakamura, H. Shibata and T. Katata, "Low Resistance Dual Damascene Process by New Al Reflow using Nb Liner", unpublished.