Intra-Node Memory Safe GPU Co-Scheduling

IEEE Transactions on Parallel and Distributed Systems

Volumn 29, Issue 5, 2018, Pages 1089-1102

  Reano, Carlos ^a   Silla, Federico ^a   Nikolopoulos, Dimitrios S ^b   Varghese, Blesson ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

accelerator; access synchronisation; GPU co scheduling; memory safe; schedGPU; under utilisation

Indexed keywords

COMPUTER GRAPHICS; GRAPHICS PROCESSING UNIT; LIBRARIES; MEMORY ARCHITECTURE; MULTITASKING; PARTICLE ACCELERATORS; PROGRAM PROCESSORS; SCHEDULING; SERVERS;

CO-SCHEDULING; MEMORY MANAGEMENT; NON-VOLATILE MEMORY; SCHEDGPU; UNDER-UTILISATION;

MEMORY MANAGEMENT UNITS;

EID: 85039762526     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2017.2784428     Document Type: Article

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