A 15 NS 32×32-bit CMOS multiplier with an improved parallel structure

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Nagamatsu, Masato ^a   Tanaka, Shigeru ^a   Mori, Junji ^a   Noguchi, Tatsuo ^a   Hatanaka, Kazuhisa ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS MULTIPLIERS; DIE AREA; METAL INTERCONNECTIONS; PARALLEL MULTIPLIERS; PARALLEL STRUCTURES; PARTIAL PRODUCT; POWER SUPPLY;

INTEGRATED CIRCUITS;

EID: 0005771573     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56842     Document Type: Conference Paper

References (7)

1. Booth, A. D., "A Signed Binary Multiplication Technique", Qt. J. Mech. Appl. Math., Vol. 4, Part 2, 1951.
2. Wallace, C. S., "A Suggestion for Fast Multipliers", IEEE Trans. Electronic Computers, Vol, EC-13, Feb. 1964, pp. 14-17.
3. J. Iwamura, et al., "A CMOS/SOS Multiplier", 1984 ISS-CC Dig. Tech. Papers, ppl94-195.
4. Y. Kaji, et al., "A 45ns 16×16 CMOS Multiplier", 1984 ISSCC Dig. Tech. Papers, pp84-85.
5. Y. Owaki, et al., "A 7.4ns CMOS 16×16 Multiplier", 1987 ISSCC Dig. Tech. Papers, pp52-53.
6. R. Sharma, et al., "A 6.75ns Single Level Metal CMOS 16×16 Multiplier", 1988 VLSI Circuits Dig. Tech. Papers, pp91-92.
7. A. E. Gamal, et al., "A CMOS 32b Wallace Tree Multiplier- Accumulator", 1986 ISSCC Dig. Tech. Papers, ppl94-195.