Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2017, Pages

  Narayanan, Pritish ^a   Sanches, Lucas L ^a   Fumarola, Alessandro ^a   Shelby, Robert M ^a   Ambrogio, Stefano ^a   Jang, Junwoo ^a   Hwang, Hyunsang ^b   Leblebici, Yusuf ^c   Burr, Geoffrey W ^a  

^a IBM ALMADEN RESEARCH CENTER   (United States)

^b Pohang University of Science and Technology (POSTECH)   (South Korea)

^c EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; BACKPROPAGATION; DATA STORAGE EQUIPMENT; DIGITAL STORAGE; LEARNING SYSTEMS; NEURONS; NONVOLATILE STORAGE; PROGRAM PROCESSORS; STOCHASTIC SYSTEMS; TIMING CIRCUITS;

CIRCUIT DESIGNS; DESIGN COMPLEXITY; MASSIVELY PARALLELS; NON-VOLATILE MEMORY; PERIPHERAL CIRCUITRY; PROGRAMMING PULSE; STOCHASTIC NATURE; TIME MULTIPLEXING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 85029492446     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2017.8050988     Document Type: Conference Paper

References (6)

1. G. W. Burr et. Al., Experimental demonstration and tolerancing of a largescale neural network (165, 000 synapses), using phase-change memory as the synaptic weight element IEDM Tech. Digest, 29. 5 2014.
2. G. W. Burr et. Al., Large-scale neural networks implemented with nonvolatile memory as the synaptic weight element: comparative performance analysis (accuracy, speed, and power) IEDM Tech. Digest, 4. 4 2015.
3. D. E. Rumelhart et. Al., A General Framework for Parallel Distributed Processing Parallel Dist Processing, MIT Press, 1986, pp. 45-76.
4. L. Kull et. Al., A 3. 1mW 8b 1. 2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOICMOSProc. of ISSCC, 26. 4 2013.
5. Y. LeCun et. Al., Gradient-Based Learning Applied to Document Recognition Proc. of IEEE, 86 (11), 1998, pp. 2278-2324.
6. H. Larochelle et. Al., An empirical evaluation of deep architectures on problems with many factors of variation Proc. of ICML., pp. 473-478 (2007).