A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 468-469

  Kull, Lukas ^a   Toifl, Thomas ^a   Schmatz, Martin ^a   Francese, Pier Andrea ^a   Menolfi, Christian ^a   Braendli, Matthias ^a   Kossel, Marcel ^a   Morf, Thomas ^a   Andersen, Toke Meyer ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CORE CHIPS; ENERGY EFFICIENT; HIGH-SPEED LINKS; MULTI-BITS; SAR ADC; SINGLE-CHANNEL; SINGLE-CHANNEL ADC; SOI CMOS;

COMPARATORS (OPTICAL);

EID: 84876531800     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487818     Document Type: Conference Paper

References (6)

1. H. Wei, C-H. Chan, U-F. Chio, et al., "A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and Resistive DAC in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 188-190, Feb. 2011
2. J. Yang, T.L. Naing, and R.W. Brodersen, "A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC using Asynchronous Processing," IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010
3. C.-H. Chan, Y. Zhu, S.-W. Sin, S.-P. U, and R. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure," IEEE Symp. VLSI Circuits, pp. 86-87, June 2012
4. Y.-C. Lien, "A 4.5-mW 8-b 750-MS/s 2-b/step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology," IEEE Symp. VLSI Circuits, pp. 88-89, June 2012
5. T. Jiang, W. Liu, F.Y. Zhong, C. Zhong, K. Hu, and P.Y. Chiang, "A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC with Improved Feedback Delay in 40-nm CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 10, Oct. 2012
6. B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: Http://www.stanford.edu/~murmann/adcsurvey.html. Accessed Nov. 17, 2012