Architecture of a synchronized low-latency network node targeted to research and education

IEEE International Conference on High Performance Switching and Routing, HPSR

Volumn 2017-June, Issue , 2017, Pages

  Lisß, Christian ^a   Ulbricht, Marian ^a   Zia, Umar Farooq ^a   Müller, Hartmut ^b  

^a Hochschule für Telekommunikation   (Germany)

^b Verilogic   (Germany)

Author keywords

FPGA based packet processing; IPv6; Low latency networking; Synchronous Ethernet; Time Sensitive Networking

Indexed keywords

DATA COMMUNICATION SYSTEMS; ETHERNET; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MACHINE-TO-MACHINE COMMUNICATION; NETWORK ARCHITECTURE;

FREQUENCY SYNCHRONIZATION; IPV6; LOW LATENCY; LOW-LATENCY NETWORKS; MOBILE ACCESS NETWORKS; NETWORKING DEVICES; PACKET PROCESSING; TIME-SENSITIVE NETWORKING;

PACKET NETWORKS;

EID: 85027285083     PISSN: 23255595     EISSN: 23255609     Source Type: Conference Proceeding    
DOI: 10.1109/HPSR.2017.7968673     Document Type: Conference Paper

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