On the influence of shared memory contention in real-time multicore applications

European Signal Processing Conference

Volumn 1998-January, Issue , 1998, Pages 25-30

  Gracioli, Giovani ^a   Fröhlich, Antônio Augusto ^a  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

Cache coherence; Contention for shared memory; Hardware performance counters; Real time multicore systems

Indexed keywords

COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; HARDWARE; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL PROCESSING; SOFTWARE ARCHITECTURE;

CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; EMBEDDED REAL-TIME APPLICATIONS; HARDWARE PERFORMANCE COUNTERS; MULTI-CORE SYSTEMS; MULTICORE ARCHITECTURES; PROCESSOR TECHNOLOGY; SHARED MEMORY;

CACHE MEMORY;

EID: 85019549159     PISSN: 22195491     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/sbesc.2014.8     Document Type: Conference Paper

References (22)

1. H. Cho, B. Ravindran, and E. D. Jensen. An optimal real-time scheduling algorithm for multiprocessors. In RTSS '06, pages 101-110. IEEE, 2006.
2. S.P. Muralidhara, M. Kandemir, and P. Raghavan. Intra-application cache partitioning. In IPDPS 10', pages 1-12, 2010.
3. Sergey Zhuravlev, Sergey Blagodurov, and Alexandra Fedorova. Addressing shared resource contention in multicore processors via scheduling. In ASPLOS '10, pages 129-142, 2010.
4. Lars Wehmeyer and Peter Marwedel. Influence of memory hierarchies on predictability for time constrained embedded software. In DATE '05, pages 600-605, Washington, DC, USA, 2005. IEEE Computer Society.
5. Vivy Suhendra and Tulika Mitra. Exploring locking & partitioning for predictable shared caches on multi-cores. In DAC '08, pages 300-303, New York, NY, USA, 2008. ACM.
6. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whal-ley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstrom. The worst-case execution-time problem overview of methods and survey of tools. ACM TECS, 7:36:1-36:53, May 2008.
7. John M. Calandrino and James H. Anderson. On the design and implementation of a cache-aware multicore real-time scheduler. In EUROMICRO'09, pages 194-204, Washington, DC, USA, 2009. IEEE.
8. R.I. Davis and A. Burns. A survey of hard real-time scheduling algorithms and schedulability analysis techniques for multiprocessor systems. techreport YCS-2009-443, University of York, 2009.
9. Silas Boyd-Wickizer, Austin T. Clements, Yandong Mao, Aleksey Pesterev, M. Frans Kaashoek, Robert Morris, and Nickolai Zeldovich. An Analysis of Linux Scalability to Many Cores. In OSDI 2010.
10. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 4th Ed., September 2006.
11. AMD. Amd64 architecture programmers manual volume 2: System programming, June 2010. Publication # 24593. revision: 3.17.
12. Intel. An introduction to the intel quickpath interconnect, January 2009. Document Number: 320412-001US.
13. B. Sprunt. Pentium 4 performance-monitoring features. IEEE Micro, 22(4):72-82, Jul/Aug 2002.
14. M. Tim Jones. Inside the linux 2.6 completely fair scheduler, December 2009 [Accessed: 02 Mar. 2011].
15. Intel Corporation. Intel® 64 and IA-32 Architectures Software Developer's Manual. Number 253668-037US. January 2011.
16. D. Tam, R. Azimi, and M. Stumm. Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors. SIGOPS Ope. Sys. Rev., 41:47-58, March 2007.
17. S. Cho and L. Jin. Managing distributed, shared l2 caches through os-level page allocation. In MICRO '06, pages 455-468, Washington, DC, USA, 2006. IEEE Computer Society.
18. Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, and Abhik Roychoud-hury. Timing analysis of concurrent programs running on shared cache multi-cores. In RTSS '09, pages 57-67, Washington, DC, USA, 2009.
19. Andrea B. and B. B. Brandenburg J. H. Anderson. Cache-related preemption and migration delays: Empirical approximation and impact on schedulability. In OSPERT '10, pages 33-44, Brussels, Jul 2010.
20. Frank Bellosa and Martin Steckermeier. The performance implications of locality information usage in shared-memory multiprocessors. Journal of Par. Dist. Comp., 37:113-121, August 1996.
21. R. West, P. Zaroo, C. A. Waldspurger, and X. Zhang. Online cache modeling for commodity multicore processors. SIGOPS Oper. Sys. Rev., 44:19-29, December 2010.
22. Nan Guan, Martin Stigge, Wang Yi, and Ge Yu. Cache-aware scheduling and analysis for multicores. In EMSOFT '09, pages 245-254, New York, NY, USA, 2009. ACM.