A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 60, Issue , 2017, Pages 242-243

  Whatmough, Paul N ^a   Lee, Sae Kyu ^a   Lee, Hyunkwang ^a   Rama, Saketh ^a   Brooks, David ^a   Wei, Gu Yeon ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP NEURAL NETWORKS; ENERGY EFFICIENCY; ERROR CORRECTION; ERRORS; LEARNING SYSTEMS; NEURAL NETWORKS; SYSTEM-ON-CHIP; TIMING CIRCUITS;

CLASSIFICATION TASKS; FLEXIBLE SUPPORTS; INTERNET OF THINGS (IOT); IOT APPLICATIONS; MEMORY RESOURCES; SPECIALIZED HARDWARE; SPIKING NEURAL NETWORKS; VIOLATION DETECTIONS;

INTERNET OF THINGS;

EID: 85016314952     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2017.7870351     Document Type: Conference Paper

References (5)

1. D. Bull, et al., "A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT variation", ISSCC, pp. 284-285, 2010.
2. P. N. Whatmough, et al., "A Low-Power 1GHz Razor FIR Accelerator with Time-Borrow Tracking Pipeline and Approximate Error Correction in 65nm CMOS", ISSCC, pp. 428-429, 2013.
3. Y. Chen, et al., "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks", ISSCC, pp. 262-263, Feb. 2016.
4. J. Kim, et al., "A 640M Pixel/s 3.65mW Sparse Event-Driven Neuromorphic Object Recognition Processor with On-Chip Learning", IEEE Symp. VLSI Circuits, 2015.
5. B. Reagen, et al., "Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators", ACM/IEEE Int. Symp. Computer Arch., pp. 267-278, 2016.