메뉴 건너뛰기




Volumn 28, Issue 1, 2009, Pages 28-34

Surveying secure processors

Author keywords

[No Author keywords available]

Indexed keywords


EID: 85008013409     PISSN: 02786648     EISSN: None     Source Type: Journal    
DOI: 10.1109/MPOT.2008.930448     Document Type: Article
Times cited : (9)

References (17)
  • 1
    • 33646909103 scopus 로고    scopus 로고
    • Hardware engines for bus encryption: A survey of existing techniques
    • R. Elbaz, et al., “Hardware engines for bus encryption: A survey of existing techniques,” in Proc. Design, Automation Test Europe Conf. Exhibition, 2005, pp. 40–45.
    • (2005) Proc. Design, Automation Test Europe Conf. Exhibition , pp. 40-45
    • Elbaz, R.1
  • 2
    • 85008027907 scopus 로고    scopus 로고
    • [Online]. Available: http://www.maximic.com/Microcontrollers.cfm
    • Dallas Semiconductor (Maxim) [Online]. Available: http://www.maximic.com/Microcontrollers.cfm
  • 3
    • 84889019266 scopus 로고    scopus 로고
    • Enhancing Security in the Memory Management Unit
    • September
    • Tanguy Gilmont, Jean-Didier Legat, and Jean Jacques Quisquater, “Enhancing Security in the Memory Management Unit,” in 25th Euromicro Conf., September 1999, Vol. 1, p. 1449.
    • (1999) 25th Euromicro Conf. , vol.1 , pp. 1449
    • Gilmont, T.1    Legat, J.-D.2    Quisquater, J.J.3
  • 4
    • 85008027385 scopus 로고    scopus 로고
    • [Online]. Available: http://www-vlsi.stanford.edu/~lie/xom.htm
    • XOM project [Online]. Available: http://www-vlsi.stanford.edu/~lie/xom.htm
  • 5
    • 1142280988 scopus 로고    scopus 로고
    • AEGIS: Architecture for tamper-evident and tamper-resistant processing
    • San Francisco
    • G. E. Suh et al., “AEGIS: Architecture for tamper-evident and tamper-resistant processing,” in Proc. Intl. Conf. Supercomputing, San Francisco, 2003, pp. 160–171.
    • (2003) Proc. Intl. Conf. Supercomputing , pp. 160-171
    • Suh, G.E.1
  • 6
    • 85008066720 scopus 로고    scopus 로고
    • A code compression method to cope with security hardware overheads, computer architecture and high performance computing, 2007
    • Eduardo Wanderley Netto, et al., “A code compression method to cope with security hardware overheads, computer architecture and high performance computing, 2007,” SBAC-PAD 2007, 19th Int. Symp., 2007, pp. 185–192.
    • (2007) SBAC-PAD 2007, 19th Int. Symp. , pp. 185-192
    • Netto, E.W.1
  • 7
    • 40349095134 scopus 로고    scopus 로고
    • Authentication control point and its implications for secure processor design
    • Weidong Shi and H.-H.S. Lee, “Authentication control point and its implications for secure processor design, in Proc. 39th Annual IEEE/ACM Int. Symp. Architecture, 2006, pp. 103–112.
    • (2006) Proc. 39th Annual IEEE/ACM Int. Symp. Architecture , pp. 103-112
    • Shi, W.1    Lee, H.-H.S.2
  • 8
    • 38949151803 scopus 로고    scopus 로고
    • Secure blue: An architecture for scalable, reliable high volume SSL Internet server
    • Ron Mraz, “Secure blue: An architecture for scalable, reliable high volume SSL Internet server,” Proc. 17th Annu. Computer Security Applications Conf., 2001, pp. 391–398.
    • (2001) Proc. 17th Annu. Computer Security Applications Conf. , pp. 391-398
    • Mraz, R.1
  • 10
    • 84944412608 scopus 로고    scopus 로고
    • Efficient memory integrity verification and encryption for secure processors
    • G.E. Suh, et al., “Efficient memory integrity verification and encryption for secure processors,” Proc., 36th Annu. IEEE/ACM Int. Symp. Microarchitecture, 2003, pp. 339–350.
    • (2003) Proc., 36th Annu. IEEE/ACM Int. Symp. Microarchitecture , pp. 339-350
    • Suh, G.E.1
  • 11
    • 17544370316 scopus 로고    scopus 로고
    • Architectural support for copy and tamper resistant software
    • David Lie, et al., “Architectural support for copy and tamper resistant software,” ACM SIGOPS Operating Syst. Rev., 2000, vol. 34, no. 5, pp. 168–177.
    • (2000) ACM SIGOPS Operating Syst. Rev. , vol.34 , Issue.5 , pp. 168-177
    • Lie, D.1
  • 12
    • 20844458580 scopus 로고    scopus 로고
    • Single-chip FPGA implementation of a cryptographic co-processor
    • F. Crowe et al., “Single-chip FPGA implementation of a cryptographic co-processor,” Proc. IEEE Int. Conf. Field-Programmable Tech., 2004 pp. 279–285.
    • (2004) Proc. IEEE Int. Conf. Field-Programmable Tech. , pp. 279-285
    • Crowe, F.1
  • 14
    • 84946422983 scopus 로고    scopus 로고
    • A design of hardware cryptographic co-processor
    • June
    • Fan Mingyu, Wang Jinahua, and Wang Guangwei, “A design of hardware cryptographic co-processor,” IEEE Syst., Man Cybern., June 2003, pp. 234–236.
    • (2003) IEEE Syst., Man Cybern. , pp. 234-236
    • Mingyu, F.1    Jinahua, W.2    Guangwei, W.3
  • 16
    • 66749160813 scopus 로고    scopus 로고
    • presented at the IEEE National Aerospace and Electronics Conference, Dayton, OH, June
    • Raghudeep Kannavara et al., “SCAN secure processor,” presented at the IEEE National Aerospace and Electronics Conference, Dayton, OH, June 2008.
    • (2008) SCAN secure processor
    • Kannavara, R.1
  • 17
    • 85008037960 scopus 로고    scopus 로고
    • [Online]. Available: http://www.intel.com/technology/security/
    • Intel® Trusted Execution Technology [Online]. Available: http://www.intel.com/technology/security/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.