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Volumn , Issue , 1999, Pages 118-122

On the fault-injection-caused increase of the DAE-Index in analogue fault simulation

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; SOFTWARE TESTING;

EID: 84992265622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.1999.804423     Document Type: Conference Paper
Times cited : (4)

References (22)
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    • June 20-22, Grenoble/Villard de Lans, France. Collection of Papers
    • I. M. Bell, S. J. Spinks: Analogue Fault Simulation for the Structural Approach to Analogue and Mixed-signal IC Testing. International Mixed Signal Testing Workshop, June 20-22, 1995, Grenoble/Villard de Lans, France. Collection of Papers, pp. 10-14.
    • (1995) International Mixed Signal Testing Workshop , pp. 10-14
    • Bell, I.M.1    Spinks, S.J.2
  • 6
    • 6144227250 scopus 로고
    • The DAE-Index in electric circuit simulation
    • Ed. I. Troch, F. Breitenecker
    • M. Günther, U. Feldmann: The DAE-Index in Electric Circuit Simulation. Proc. IMACS Symp. Mathematical Modelling. (Ed. I. Troch, F. Breitenecker) vol. 4, pp.695-702, 1994.
    • (1994) Proc. IMACS Symp. Mathematical Modelling , vol.4 , pp. 695-702
    • Günther, M.1    Feldmann, U.2
  • 7
    • 0001759516 scopus 로고    scopus 로고
    • CAD based electric circuit modeling. Part I: Mathematical structure and index of network equations
    • M. Günther, U. Feldmann: CAD based electric circuit modeling. Part I: Mathematical structure and index of network equations. Surv. Math. Ind. (1999) 8: 97-129.
    • (1999) Surv. Math. Ind , vol.8 , pp. 97-129
    • Günther, M.1    Feldmann, U.2
  • 8
    • 0001759516 scopus 로고    scopus 로고
    • CAD based electric circuit modeling. Part II: Impact of network structure and parameters
    • M. Günther, U. Feldmann: CAD based electric circuit modeling. Part II: Impact of network structure and parameters. Surv. Math. Ind. (1999) 8: 131-157.
    • (1999) Surv. Math. Ind , vol.8 , pp. 131-157
    • Günther, M.1    Feldmann, U.2
  • 12
    • 85040042811 scopus 로고    scopus 로고
    • 4. GMM/ITG Diskussionssitzung - Entwicklung von Analogschaltungen mit CAE-Methoden, Berlin, Oktober, S. 101 - 108
    • K. Matz, C. Clauß: Zur Simulationspraxis bei DAE's mit höherem Index. 4. GMM/ITG Diskussionssitzung - Entwicklung von Analogschaltungen mit CAE-Methoden, Berlin, Oktober 1997, S. 101 - 108.
    • (1997) Zur Simulationspraxis Bei DAE's mit Höherem Index
    • Matz, K.1    Clauß, C.2
  • 14
    • 85040040521 scopus 로고    scopus 로고
    • Graphentheoretische bestimmung des strukturellen index von algebro-differential- gleichungssystemen für die netzwerkanalyse
    • In W. Mathis, P. Noll (Hrsg.):, ITG-Diskussionssitzung vom 21.-22. April 1995 in Berlin, S. 207-214, VDE-Verlag
    • K. Reinschke, K. Röbenack: Graphentheoretische Bestimmung des strukturellen Index von Algebro-Differential- Gleichungssystemen für die Netzwerkanalyse. In W. Mathis, P. Noll (Hrsg.): Neue Anwendungen theoretischer Konzepte in der Elektrotechnik - Tagungsberichte der 2. ITG-Diskussionssitzung vom 21.-22. April 1995 in Berlin, S. 207-214, VDE-Verlag, 1996.
    • (1996) Neue Anwendungen Theoretischer Konzepte in Der Elektrotechnik - Tagungsberichte Der 2
    • Reinschke, K.1    Röbenack, K.2
  • 15
    • 0038911565 scopus 로고    scopus 로고
    • Graph-Theoretically determined Jordan block size structure of regular matrix pencils
    • K. Röbenack, K. Reinschke: Graph-Theoretically determined Jordan block size structure of regular matrix pencils, Linear Algebra Appl. 263 (1997), 333-348.
    • (1997) Linear Algebra Appl , vol.263 , pp. 333-348
    • Röbenack, K.1    Reinschke, K.2
  • 16
    • 0029696453 scopus 로고    scopus 로고
    • Computing the generic index of the circuit equations of linear active networks
    • Altanta, 12-15. Mai 1996, Band III, S
    • G. Reißig, U. Feldmann: Computing the generic index of the circuit equations of linear active networks. In Proc. Int. Symp. on Circuits and Systems (ISCAS), Altanta, 12-15. Mai 1996, Band III, S. 190-193.
    • Proc. Int. Symp. on Circuits and Systems (ISCAS) , pp. 190-193
    • Reißig, G.1    Feldmann, U.2
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  • 19
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    • Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits
    • Paris, France, March 6 - 9, 1995
    • Chr. Sebeke, J. P. Teixeira, M. J. Ohletz: Automatic Fault Extraction and Simulation of Layout Realistic Faults for Integrated Analogue Circuits. European Design and Test Conference 1995, Paris, France, March 6 - 9, 1995, pp. 464-468.
    • (1995) European Design and Test Conference , pp. 464-468
    • Sebeke, C.1    Teixeira, J.P.2    Ohletz, M.J.3
  • 22
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    • A suggestion for accelerating the analogue fault simulation
    • Paris, France, Feb. 28 - March 3, IEEE Comp. Society Press, Los Alamitos, CA
    • W. Vermeiren, B. Straube, G. Elst: A Suggestion for Accelerating the Analogue Fault Simulation. In: Proc. EDAC-ETC-EUROASIC 1994, Paris, France, Feb. 28 - March 3, p. 662, IEEE Comp. Society Press, Los Alamitos, CA, 1994.
    • (1994) Proc. EDAC-ETC-EUROASIC 1994 , pp. 662
    • Vermeiren, W.1    Straube, B.2    Elst, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.