Compiler-Assisted Workload Consolidation for Efficient Dynamic Parallelism on GPU

Proceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016

Volumn , Issue , 2016, Pages 534-543

  Wu, Hancheng ^a   Li, Da ^a   Becchi, Michela ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

Consolidation; Dynamic Parallelism; GPU; Irregular Computations

Indexed keywords

CONSOLIDATION; COSINE TRANSFORMS; MASKS; PROGRAM COMPILERS; PROGRAM PROCESSORS;

CODE TRANSFORMATION; COMPILER-ASSISTED; DEGREE OF PARALLELISM; HARDWARE UTILIZATION; IMPROVE PERFORMANCE; IRREGULAR COMPUTATIONS; NESTED PARALLELISM; WORKLOAD CONSOLIDATION;

COMPUTER HARDWARE;

EID: 84983239150     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2016.98     Document Type: Conference Paper

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