A CMOS 2- and 4-FSK demodulator for direct-conversion radio paging receivers

2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

Volumn 2, Issue , 2002, Pages 1289-1292

  Chen, Zhiheng ^a   Zhang, Zhaofeng ^a   Lau, J ^b  

^a SOUTHEAST UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

4 FSK demodulator; clock recovery; CMOS integrated circuits; direct conversion receiver; frequency shift keying; high speed pager; paging communication

Indexed keywords

BIT ERROR RATE; CLOCKS; DEMODULATORS; ELECTRIC CLOCKS; FREQUENCY SHIFT KEYING; RADIO RECEIVERS; RECONFIGURABLE HARDWARE; SIGNAL RECEIVERS;

BIT ERROR RATE (BER) PERFORMANCE; CLOCK RECOVERY; CLOCK RECOVERY CIRCUITS; DECISION ACCURACIES; DIRECT CONVERSION RECEIVERS; HIGH SPEED; MEASUREMENT AND SIMULATION; PAGING COMMUNICATION;

CMOS INTEGRATED CIRCUITS;

EID: 84976475852     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2002.1179018     Document Type: Conference Paper

References (13)

1. I. Vance, "An integrated circuit V.H.F. radio receiver", The Radio and Electronic Engineer, Vol. 50, No. 4, pp. 158-64, Apr. 1980.
2. I. Vance, "Fully integrated radio paging receiver", IEE Proc., Vol. 129, Pt. F, No. 1, pp. 2-6, Feb. 1982,.
3. J. Wilson, R. Youell, T. Richards, G. Luff, and R. Pilaski, "A single-chip VHF and UHF receiver for radio paging", IEEE J. Solid-State Circuits, Vol. 26, No. 12, pp. 1944-1950, Dec. 1991.
4. K. Takahashi, M. Mimura, M. Hasegawa, M. Makimoto and K. Yokozaki., "A direct conversion receiver utilizing a novel FSK demodulator and a low power consumption quadrature mixer", Vehicular Technology Society 42nd VTS Conference. (1992) p910-15 vol.2.
5. M. Saitou, M. Kawabata and Y. Akaiwa, "Direct conversion receiver for 2- and 4-level FSK signals", 4th IEEE international conference on universal personal communications, pp. 392-396, 1995.
6. M. Mimura, K. Abe, M. Hasegawa and H. Katayama, "The direct-conversion receiver for a fast multilevel FSK", IEICE Japan national spring convention B-448, Mar. 1995.
7. Z. Chen, and J. Lau, "Circuit requirements of a direct conversion paging receiver," IEEE Tran. Circuits Syst. II, Vol. 46, No. 6, pp. 802-807, June 1999.
8. T. Yamaji, H. Tanimoto and H. Kokatsu, "An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter," IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp.2240-2246, Dec. 1998.
9. Z. Zhang, Z. Chen and J. Lau, "A 900 MHz CMOS balanced harmonic mixer for direct conversion receivers," the 2000 IEEE Radio and Wireless Conference, Sep. 2000.
10. Z. Zhang, Z. Chen and J. Lau, "A 930MHz CMOS DC-Offset-Free Direct-Conversion 4-FSK Receiver," in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 290-291.
11. E. Lee, "Zero-crossing zero-IF demodulator," Electronics Letters, Vol. 31, No. 15, pp. 1218-19, July 1995.
12. H. Kwon and K. Lee, "A novel digital FM receiver for mobile and personal communications," IEEE Tran. Commun, Vol. 44, No. 11, pp. 1466-1476, Nov. 1996.
13. B. Razavi, "Design of monolithic phase-locked loops and clock recovery circuits - a tutorial," Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, New York: IEEE Press, 1996.