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Volumn 2469, Issue , 2002, Pages 83-105

An overview of formal verification for the time-triggered architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FAULT TOLERANCE; REAL TIME SYSTEMS; SAFETY ENGINEERING;

EID: 84974693449     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45739-9_7     Document Type: Conference Paper
Times cited : (35)

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