Verification of timed automata via satisfiability checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2469, Issue , 2002, Pages 225-243

  Niebert, Peter ^b   Mahfoudh, Moez ^a   Asarin, Eugene ^a   Bozga, Marius ^a   Maler, Oded ^a   Jain, Navendu ^c  

^a VERIMAG   (France)

^b AIX MARSEILLE UNIV   (France)

^c INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; FAULT TOLERANCE; FORMAL LOGIC; REAL TIME SYSTEMS;

PROPOSITIONAL LOGIC; SATISFIABILITY CHECKER; SATISFIABILITY CHECKING; TIMED AUTOMATA; TIMING CONSTRAINTS; VERIFICATION PROBLEMS;

COMPUTER CIRCUITS;

EID: 84974666943     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45739-9_15     Document Type: Conference Paper

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