On the test and diagnosis of the perfect shufe

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 97-104

  Schiano, L ^a   Lombardi, F ^a  

^a Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX NETWORKS; DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT INTERCONNECTS; TESTING;

GRAPH COLORINGS; MULTISTAGE INTERCONNECTION NETWORK; SHORT FAULT; STRUCTURAL APPROACH; STUCK-AT FAULTS; SWITCHING OPERATIONS; TEST GENERATION ALGORITHM; TESTABILITY;

FAULT DETECTION;

EID: 84971290784     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250100     Document Type: Conference Paper

References (20)

1. S. Melvin, M. Nemirovsky, E. MusoH, J. Huynh, R. Molito, H. Urdaneta, K. Sarad, "A Massively Multithreaded Packet Processors", Proc. IEEE Workshop on Network Processors, pp. 64-74, 2003.
2. W.-T. Cheng, J. Lewandowski, E. Wu, "Diagnosis for Wiring Interconnects", Int. Test Conj, pp. 565-571, 1990.
3. A. J. Hassan, J. Rajski and V. K. Agrawal, "Testing and Diagnosis of Interconnects using Boundary-scan", International Test Conference, pp. 126-137, 1988.
4. W. Kautz, "Testing for Fault in Wiring Networks", IEEE Tans on Comp, Vol. C-23, No. 4, pp. 358-363, 1974.
5. T. Liu, F. Lombardi, and J. Salinas, "Diagnosis of Interconnects and FPICs using a Structured Walking-1 Approach", Proc. IEEE VLSI Test Symposium, pp. 256-261, 1995.
6. P. T. Wagner, "Interconnect Testing with Boundary Scan", International Test Conference, pp. 52-57, 1987.
7. C. W. Yau, and N. Jarwala, "A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects", Interational Test Confernce, pp. 71-77, 1989.
8. V. Betz and J. Rose, "Automatic Generation of FPGA Routing Architectures From High-Level Descriptions", in Proc. ACM Int. Symp. on FPGAs, pp. 175-186, 2000.
9. Y.-W. Chang, D. F. Wong, and C. K. Wong, "Universal Switch-Module Design for Symmetric-Array-Based FPGAs", in Proc. ACM Int. Symp. on FPGAs, pp. 80-86, 1996.
10. C. Wu, and T. Feng, "Fault Diagnosis for a Class of Multistage Interconnection Networks", IEEE Trans. on Compllt. Vol. C30, No. 10, pp. 743-758, 1981.
11. F. Lombardi, and W.-K. Huang, "On The Constant Diagnosability of Baseline Interconnection Networks", IEEE Tans. on Compllt. vol. C39, no. 12, pp. 1485-1488, 1990.
12. C. Feng, F. Lombardi and W.-K. Huang, "Detection and Location of Multiple Faults in Baseline Interconnection Networks", IEEE Tansactions on Computers, vol. C41, no. 11, pp. 1340-1344, 1992.
13. T. H. Cormen, C. E. Leiserson and R. L. Rivest, Introdllction To Algorithms, McGraw-Hill, pp. 579-629, 1990.
14. J. V. Leeuwen, Handbook of Theoretical Compllter Science, Cambridge: MIT Press, Vol. A, pp. 591-592, 1990.
15. J. Rose and S. Brown, "Flexibility of Interconnection Structure for Field Programmable Gate Arrays", IEEE J. Solid-State Circll its, vol. 26, no. 13, pp. 277-282, 1991.
16. M. Patyra, and W. Maly, "Circuit DeSign for a Large Area High Performance Crossbar Switch", Proc. IEEE Int. Workshop on DFT on VLSI Systems, pp. 32-45, 1991.
17. A. Mourad, B. Ozden and M. Malek, "Comprehensive Testing of Multistage Interconnection Networks", IEEE Trans. on Compllt., Vol. C40, No. 8, pp. 935-951, 1991.
18. J. D. Ullman, "Computational Aspects of VLSI", Computer Science Press, Rockville, Md., 1984.
19. M. Gries, C. Kulkarni, C. Sauer and K. Keutzer, "Exploring Tade-ofs in Performance and Programmability of Processing Element Topologies for Network Processors", Proc. IEEE Workshop on Net. Proc., pp. 75-87, 2003.
20. Y. Chen, D. Lawrie, D. Padua and P. Yew, "Interconnection Networks Using Shufes", IEEE Compllter, Vol. 14, No. 12, pp 55-65, 1981.