Solving satisfiability in combinational circuits with backtrack search and recursive learning

Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999

Volumn , Issue , 1999, Pages 192-195

  Marques Silva, João P ^a   Guerra E Silva, Luís Guerra ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; ELECTRONIC DESIGN AUTOMATION; FORMAL LOGIC; INTEGRATED CIRCUITS; ITERATIVE METHODS; SYSTEMS ANALYSIS; TIMING CIRCUITS;

ALGORITHMIC FRAMEWORK; BOOLEAN SATISFIABILITY; CIRCUIT STRUCTURES; DELAY-FAULT TESTING; EQUIVALENCE CHECKING; PRUNING TECHNIQUES; RECURSIVE LEARNING; TEST PATTERN GENERATIONS;

DELAY CIRCUITS;

EID: 84968426498     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.1999.803118     Document Type: Conference Paper

References (14)

1. M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
2. R. Bayardo Jr. and R. Schrag, "Using CSP Look-Back Techniques to Solve Real-World SAT Instances, " in Proc. of the National Conf. on Artificial Intelligence, pp. 203-208, July 1997.
3. L. Guerra e Silva et al., "Algorithms for Solving Boolean Satisfiability in Combinational Circuits, " in Proc. of the Design, Automation and Test in Europe Conf., March 1999.
4. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publishers, 1996.
5. S.-Y. Huang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging, Kluwer Academic Publishers, 1998.
6. W. Kunz and D. Stoffel, Reasoning in Boolean Networks, Kluwer Academic Publishers, 1997.
7. T. Larrabee, "Test Pattern Generation Using Boolean Satisfiability, " IEEE Trans. on Computer-Aided Design, vol. 11, no. 1, pp. 4-15, January 1992.
8. J. Marques-Silva and K. A. Sakallah, "GRASP-A New Search Algorithm for Satisfiability, " in Proc. Proc.of the Intl. Conf. on Computer-Aided Design, pp. 220-227, November 1996.
9. J. Marques-Silva and T. Glass, "Combinational Equivalence Checking Using Satisfiability and Recursive Learning, " in Proc. of the Design, Automation and Test in Europe Conf., March 1999.
10. J. Marques-Silva and L. Guerra e Silva, "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning, " in Intl. Workshop on Logic Synthesis, June 1999.
11. P. McGeer et al., "Timing Analysis and Delay-Test Generation Using Path Recursive Functions, " in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 180-183, November 1991.
12. P. Stephan et al., "Combinatorial Test Generation Using Satisfiability", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, Sep. 1996.
13. P. Tafertshofer et al., "A SAT-Based Implication Engine for Efficient ATPG, Equivalence Checking., Optimization of Netlists, " in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 648-657, November 1997.
14. H. Zhang, "SATO: An Efficient Propositional Prover, " in Proc. of Intl. Conf. on Automated Deduction, pp. 272-275, July 1997.