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Volumn , Issue , 2002, Pages 171-176

Efficient pipelining of nested loops: Unroll-and-squash

Author keywords

[No Author keywords available]

Indexed keywords


EID: 84966587878     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2002.1015491     Document Type: Conference Paper
Times cited : (20)

References (15)
  • 3
    • 0032308182 scopus 로고    scopus 로고
    • Cords: Hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
    • R. Dick, and N. Jha. Cords: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems, Proc. Intl. Conference on Computer-Aided Design, 1998.
    • (1998) Proc. Intl. Conference on Computer-Aided Design
    • Dick, R.1    Jha, N.2
  • 4
    • 0032681537 scopus 로고    scopus 로고
    • An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications
    • M. Kaul, et al. An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications, Proc. 36th Design Automation Conference, 1999.
    • (1999) Proc. 36th Design Automation Conference
    • Kaul, M.1
  • 5
    • 84966500218 scopus 로고
    • Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
    • M. Gokhale, and A. Marks. Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays, Proc. FPL, 1995.
    • (1995) Proc. FPL
    • Gokhale, M.1    Marks, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.