VOCL-FT: Introducing techniques for efficient soft error coprocessor recovery

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Volumn 15-20-November-2015, Issue , 2015, Pages

  Peña, Antonio J ^a   Bland, Wesley ^a   Balaji, Pavan ^a  

^a ARGONNE NATIONAL LABORATORY   (United States)

Author keywords

co processor; ECC; fault tolerance; virtualization; VOCL

Indexed keywords

DATA TRANSFER; DIGITAL STORAGE; FAULT TOLERANCE; RADIATION HARDENING; SEMANTICS;

ACCELERATOR PROGRAMMING; CO-PROCESSORS; FAULT TOLERANT SYSTEMS; OFFLOADING COMPUTATIONS; PROGRAMMING MODELS; SYNCHRONIZATION POINTS; VIRTUALIZATIONS; VOCL;

ERRORS;

EID: 84966487041     PISSN: 21674329     EISSN: 21674337     Source Type: Conference Proceeding    
DOI: 10.1145/2807591.2807640     Document Type: Conference Paper

References (31)

1. W. Bland, A. Bouteiller, T. Herault, G. Bosilca, and J. Dongarra. Post-failure recovery of MPI communication capability: Design and rationale. International Journal of High Performance Computing Applications, 27(3):244-254, 2013.
2. G. Bosilca, R. Delmas, J. Dongarra, and J. Langou. Algorithm-based fault tolerance applied to high performance computing. Journal ofParallel and Distributed Computing, 69(4):410-416, 2009.
3. A. Bouteiller, F. Cappello, T. Herault, K. Krawezik, P. Lemarinier, and M. Magniette. MPICH-V2: a fault tolerant MPI for volatile nodes based on pessimistic sender based message logging. In ACM/IEEE Supercomputing Conference, Nov. 2003.
4. A. Castello, J. Duato, R. Mayo, A. J. Pefia, E. S. Quintana-Orti, V. Roca, and F. Silla. On the use of remote GPUs and low-power processors for the acceleration of scientific applications. In International Conference on Smart Grids, Green Communications and IT Energy-aware Technologies (ENERGY), 2014.
5. J. Chung, I. Lee, M. Sullivan, J. H. Ryoo, D. W. Kim, D. H. Yoon, L. Kaplan, and M. Erez. Containment domains: A scalable, efficient and flexible resilience scheme for exascale systems. Scientific Programming, 21(3-4):197-212, 2013.
6. L. B. Gomez, F. Cappello, L. Carro, N. DeBardeleben, B. Fang, S. Gurumurthi, K. Pattabiraman, P. Rech, and M. S. Reorda. GPGPUs: how to combine high computational power with high reliability. In Design, Automation & Test in Europe (DATE), 2014.
7. P. H. Hargrove and J. C. Duell. Berkeley Lab Checkpoint/Restart (BLCR) for Linux clusters. Journal ofPhysics: Conference Series, 46(1):494, 2006.
8. M. A. Heroux, D. W. Doerfler, P. S. Crozier, J. M. Willenbring, H. C. Edwards, A. Williams, M. Rajan, E. R. Keiter, H. K. Thornquist, and R. W. Numrich. Improving performance via mini-applications. Technical report, Sandia National Laboratories, 2009.
9. Intel Corporation. Intel MPI library. http://software.intel.com/en-us/intel-mpi-library, 2015.
10. A. Kawai, K. Yasuoka, K. Yoshikawa, and T. Narumi. Distributed-Shared CUDA: Virtualization of large-scale GPU systems for programmability and reliability. In International Conference on Future Computational Technologies and Applications, 2012.
11. J. Kim, S. Seo, J. Lee, J. Nah, G. Jo, and J. Lee. SnuCL: an OpenCL framework for heterogeneous CPU/GPU clusters. In 26th International Conference on Supercomputing, pages 341-352. ACM, 2012.
12. P. Lama, Y. Li, A. M. Aji, P. Balaji, J. Dinan, S. Xiao, Y. Zhang, W. Feng, R. Thakur, and X. Zhou. pVOCL: Power-aware dynamic placement and migration in virtualized GPU environments. In 33rd International Conference on Distributed Computing Systems (ICDCS), pages 145-154. IEEE, 2013.
13. P. Lavallee, G. C. de Verdiere, P. Wautelet, D. Lecas, and J. Dupays. Porting and optimizing HYDRO to new platforms and programming paradigms-lessons learnt. Technical report, PRACE, Dec. 2012.
14. A. Munshi, editor. The OpenCL Specification Version 2.0. Khronos OpenCL Working Group, 2014.
15. R. Naseer and J. Draper. Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. In 34th European Solid-State Circuits Conference (ESSCIRC), pages 222-225, Sept. 2008.
16. NVIDIA Corporation. NVIDIA Management Library (NVML). http://developer.nvidia.com/nvidia-management-library-nvml, 2015.
17. A. J. Pena. Virtualization of accelerators in high performance clusters. PhD thesis, Universitat Jaume I, Castellon, Spain, Jan. 2013.
18. A. J. Penia and S. R. Alam. Evaluation of inter-and intra-node data transfer efficiencies between GPU devices and their impact on scalable applications. In 13th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid), 2013.
19. A. J. Pena, C. Reafio, F. Silla, R. Mayo, E. S. Quintana-Orti, and J. Duato. A complete and efficient CUDA-sharing solution for HPC clusters. Parallel Computing, 40(10):574-588, 2014.
20. M. Rebaudengo, M. Reorda, M. Torchiano, and M. Violante. Soft-error detection through software fault-tolerance techniques. In International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pages 210-218, Nov 1999.
21. A. Rezaei, G. Coviello, C. Li, S. Chakradhar, and F. Mueller. Snapify: capturing snapshots of offload applications on Xeon Phi manycore processors. In International Symposium on High-Performance Parallel and Distributed Computing. ACM, 2014.
22. S. Sankaran, J. M. Squyres, B. Barrett, V. Sahay, A. Lumsdaine, J. Duell, P. Hargrove, and E. Roman. The LAM/MPI checkpoint/restart framework: System-initiated checkpointing. International Journal of High Performance Computing Applications, 19(4):479-493, 2005.
23. E. Strohmaier, J. Dongarra, H. Simon, and M. Meuer. TOP500 supercomputing sites. http://www.top500.org/lists/2014/11, Nov. 2014.
24. H. Takizawa, K. Koyama, K. Sato, K. Komatsu, and H. Kobayashi. CheCL: Transparent checkpointing and process migration of OpenCL applications. In International Parallel & Distributed Processing Symposium (IPDPS), pages 864-876. IEEE, 2011.
25. H. Takizawa, K. Sato, K. Komatsu, and H. Kobayashi. CheCUDA: A checkpoint/restart tool for CUDA applications. In International Conference on Parallel and Distributed Computing, Applications and Technologies, pages 408-413. IEEE, 2009.
26. TSUBAME Computing Services. Failure history of TSUBAME2.5. http://mon.g.gsic.titech.ac.jp/trouble-list, 2015.
27. Virginia Tech. HokieSpeed (Seneca CPU-GPU). http://www.arc.vt.edu/resources/hpc/hokiespeed.php, 2015.
28. J. Wadden, A. Lyashevsky, S. Gurumurthi, V. Sridharan, and K. Skadron. Real-world design and evaluation of compiler-managed GPU redundant multithreading. In International Symposium on Computer Architecture (ISCA), pages 73-84, 2014.
29. C. Wilkerson, A. R. Alameldeen, Z. Chishti, W. Wu, D. Somasekhar, and S. Lu. Reducing cache power with low-cost, multi-bit error-correcting codes. SIGARCH Comput. Archit. News, 38(3):83-93, 2010.
30. S. Xiao, P. Balaji, Q. Zhu, R. Thakur, S. Coghlan, H. Lin, G. Wen, J. Hong, and W. Feng. VOCL: An optimized environment for transparent virtualization of graphics processing units. In Innovative Parallel Computing (InPar). IEEE, 2012.
31. K. S. Yim, C. Pham, M. Saleheen, Z. Kalbarczyk, and R. Iyer. Hauberk: Lightweight silent data corruption error detector for GPGPU. In International Conference on Parallel and Distributed Computing, Applications and Technologies, pages 287-300, 2011.