An all-digital PLL clock multiplier

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Volumn , Issue , 2002, Pages 275-278

  Olsson, T ^a   Nilsson, P ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; MULTIPLYING CIRCUITS;

ALL-DIGITAL PLL; CLOCK MULTIPLIERS; DIGITAL STANDARDS; FREQUENCY RANGES; FULLY INTEGRATED; OFF-CHIP COMPONENTS; STANDARD CMOS PROCESS; SUPPLY VOLTAGES;

DIGITAL LIBRARIES;

EID: 84966309399     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.2002.1031585     Document Type: Conference Paper

References (3)

1. P. Nilsson and M. Torkelson, "A Monolitic Digital Clock-Generator for On-Chip Clocking of Custom DSP's", IEEE J. Solid-State Circuits, vol.31, No. 5, pp. 700-706, May. 1996.
2. T. Olsson, P. Nilsson, T. Meincke, A. Hemani and M. Torkelson. "A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs", In Proceedings of ISCAS'2000, Geneva, May 2000.
3. R. E. Best, Phase-locked loops, McGraw-Hill, 1984.