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Volumn , Issue , 2002, Pages 101-106

A software fault tolerance method for safety-critical systems: Effectiveness and drawbacks

Author keywords

[No Author keywords available]

Indexed keywords

FAULT DETECTION; INTEGRATED CIRCUITS; RADIATION EFFECTS; RECONFIGURABLE HARDWARE; SAFETY ENGINEERING; SAFETY TESTING; SYSTEMS ANALYSIS;

EID: 84965156298     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2002.1137644     Document Type: Conference Paper
Times cited : (27)

References (10)
  • 1
    • 0016522101 scopus 로고
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    • B. Randell, "System Structure for Software Fault Tolerant," IEEE Trans. On Software Engineering, Vol. 1, No. 2, Jun. 1975, pp. 220-232
    • (1975) IEEE Trans. on Software Engineering , vol.1 , Issue.2 , pp. 220-232
    • Randell, B.1
  • 2
    • 0028727191 scopus 로고
    • Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits
    • R. Velazco, D. Bessot, R. Eccofet, S. Duzellier, Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits, IEEE Transactions on Nuclear Science, Vol. 6, no 41, 1994, pp. 2229-2234
    • (1994) IEEE Transactions on Nuclear Science , vol.6 , Issue.41 , pp. 2229-2234
    • Velazco, R.1    Bessot, D.2    Eccofet, R.3    Duzellier, S.4
  • 3
    • 0024169259 scopus 로고
    • An SEU Hardened CMOS Data Latch Design
    • Dec.
    • L. Rockett, "An SEU Hardened CMOS Data Latch Design", IEEE Trans. On Nuclear Science, Vol. 35, No.6, Dec. 1988
    • (1988) IEEE Trans. on Nuclear Science , vol.35 , Issue.6
    • Rockett, L.1
  • 4
    • 0002901176 scopus 로고
    • Low Power SEU Immune CMOS Memory Circuits
    • Dec.
    • M. N. Liu and S Witaker, "Low Power SEU Immune CMOS Memory Circuits", IEEE Trans. On Nuclear Science, Vol. 39, No.6, Dec. 1992, pp. 1679-1684
    • (1992) IEEE Trans. on Nuclear Science , vol.39 , Issue.6 , pp. 1679-1684
    • Liu, M.N.1    Witaker, S.2
  • 5
    • 0032684765 scopus 로고    scopus 로고
    • Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
    • M. Nicolaidis, "Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies", VTS'99: IEEE VLSI Test Symposium, 1999, pp. 86-94
    • (1999) VTS'99: IEEE VLSI Test Symposium , pp. 86-94
    • Nicolaidis, M.1
  • 6
    • 0021439162 scopus 로고
    • Algorithm-Based Fault Tolerance for Matrix Operations
    • December
    • K. H. Huang, J. A. Abraham, "Algorithm-Based Fault Tolerance for Matrix Operations", IEEE Trans. on Computers, vol. 33, December 1984, pp. 518-528
    • (1984) IEEE Trans. on Computers , vol.33 , pp. 518-528
    • Huang, K.H.1    Abraham, J.A.2
  • 8
    • 0000347178 scopus 로고
    • An Approach to Concurrent Control Flow Checking
    • March
    • S.S. Yau, F.-C. Chen, "An Approach to Concurrent Control Flow Checking," IEEE Trans. On Software Engineering, Vol. 6, No. 2, March 1980, pp. 126-137
    • (1980) IEEE Trans. on Software Engineering , vol.6 , Issue.2 , pp. 126-137
    • Yau, S.S.1    Chen, F.-C.2
  • 10
    • 0002852824 scopus 로고    scopus 로고
    • THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment
    • Spain, 27-29 May
    • Velazco R., Cheynet Ph., Bofill A., Ecoffet R., "THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment", IEEE European Test Workshop (ETW'98), Spain, 27-29 May 1998
    • (1998) IEEE European Test Workshop (ETW'98)
    • Velazco, R.1    Cheynet, Ph.2    Bofill, A.3    Ecoffet, R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.