NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 17.1.1-17.1.4

  Kim, S ^a   Ishii, M ^b   Lewis, S ^a   Perri, T ^d   Brightsky, M ^a   Kim, W ^a   Jordan, R ^d   Burr, G W ^c   Sosa, N ^a   Ray, A ^a   Han, J P ^a   Miller, C ^a   Hosokawa, K ^b   Lam, C ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH TOKYO   (Japan)

^c IBM ALMADEN RESEARCH CENTER   (United States)

^d Mixed Signal ICs Department   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; LEARNING ALGORITHMS; NEURONS; RECONFIGURABLE HARDWARE; TIMING CIRCUITS;

CIRCUIT IMPLEMENTATION; IN-SITU LEARNING; INTEGRATE AND FIRES; LEARNING PATHS; NEURON CIRCUITS; PHASE CHANGE MEMORY (PCM); SPIKE TIMING DEPENDENT PLASTICITIES; SYNAPTIC WEIGHT;

PHASE CHANGE MEMORY;

EID: 84964033683     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409716     Document Type: Conference Paper

References (10)

1. P. Merolla et al., Science, vol.345, no. 6197, pp. 668-673, 2014.
2. N. D. Lane et al., 2015 HotMobile, pp.117-122.
3. H.-S. P. Wong et al., Proc. IEEE, vol. 98, no. 12, pp. 2201-2227, 2010.
4. D. Kuzum et al., Nanotechnology, vol. 24, no. 38, p. 382001, 2013.
5. M. Boniardi et al., 2014 IEDM, pp. 29.1-4.
6. S. Kim and C. Lam, "Neuromorphic memory circuit", U.S. patent application, filed on 24 Jun 2015 (priority date 14 Jan 2015).
7. Z. Wang et al., Front. Neurosci., vol. 8, pp. 438.1-11, 2015.
8. B. L. Jackson et al., ACM J. Emerg. Technol. Comput. Syst., vol. 9, no. 2, pp. 121-1220, 2013.
9. T. Brancon et al., Science, vol. 329, no. 5999, pp. 1671-1675, 2010.
10. Peter Földiák, "Sparse coding in the primate cortex," in The Handbook of Brain Theory and Neural Networks, 2nd ed., The MIT Press, 2002, pp. 1064-1068.