The shift to multicores in real-time and safety-critical systems

2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015

Volumn , Issue , 2015, Pages 220-229

  Saidi, Selma ^a   Ernst, Rolf ^a   Uhrig, Sascha ^b   Theiling, Henrik ^c   De Dinechin, Benoît Dupont ^d  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

^b AIRBUS GROUP INNOVATIONS   (Germany)

^c Sysgo AG   (Germany)

^d Kalray SA   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; HARDWARE; HARDWARE-SOFTWARE CODESIGN; MULTICORE PROGRAMMING; RECONFIGURABLE HARDWARE; SAFETY ENGINEERING; SECURITY SYSTEMS;

MULTI-CORE PLATFORMS; MULTI-CORE SYSTEMS; PARALLEL SOFTWARE; REAL-TIME COMMUNITY; REALTIME BEHAVIORS; SAFETY CRITICAL SYSTEMS; SOFTWARE IMPLEMENTATION; SYSTEM DEVELOPMENT;

REAL TIME SYSTEMS;

EID: 84963717401     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CODESISSS.2015.7331385     Document Type: Conference Paper

References (24)

1. F. Boniol New challenges for future avionic architectures A. Amine, O. A. Mohamed, and L. Bellatreche, editors, Modeling Approaches and Algorithms for Advanced Computer Applications 488 of Studies in Computational Intelligence, page 1 Springer 2013 ISBN 978-3-319-00559-1, http://dx.doi.org/10.1007/978-3-319-00560-7-1
2. F. Certification Authorities Software Team (CAST). Position paper cast-32, multi-core processors, May 2014. URL http://www.faa.gov/aircraft/air-cert#/design- approvals/air-software/cast/cast-papers/media/cast-32.pdf.
3. R. L. Cruz. A calculus for network delay, part i: Network elements in isolation. IEEE Trans. on Information Theory, 37(1):114-131, 1991.
4. B. D. de Dinechin, Y. Durand, D. van Amstel, and A. Ghiti. Guaranteed services of the noc of a manycore processor. In Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc 14, pages 11-16, New York, NY, USA, 2014. ACM. ISBN 978-1-4503-3064-0. . URL http://doi.acm.org/10.1145/2685342.2685344.
5. B. D. de Dinechin, D. van Amstel, M. Poulhìes, and G. Lager. Timecritical computing on a single-chip massively parallel processor. In Proceedings of the Conference on Design, Automation & Test in Europe, DATE 14, pages 97:1-97:6, 3001 Leuven, Belgium, Belgium, 2014. European Design and Automation Association. ISBN 978-3-9815370-2-4. URL http://dl.acm.org/citation.cfm? id=2616606.2616725.
6. B. Dupont de Dinechin, Y. Durand, D. van Amstel, and A. Ghiti. Guaranteed services of the noc of a manycore processor. In Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc 14, pages 11-16, New York, NY, USA, 2014. ACM. ISBN 978-1-4503-3064-0. .
7. G. Durrieu, M. Faugere, S. Girbal, D. Gracia Pãrez, C. Pagetti, and W. Puffitsch. Predictable flight management system implementation on a multicore processor. In Embedded Real Time Software and Systems, ERTS 14, 2014. URL http://www.erts2014.org/Site/0R4UXE94/Fichier/erts2014-2A1.pdf.
8. EASA. Certification memorandum-development assurance of airborne electronic hardware. In Software and Complex Electronic Hardware section, chapter 9. European Aviation Safety Agency, 11th Aug 2011.
9. D. R. Engler, M. F. Kaashoek, and J. OToole, Jr. Exokernel: An operating system architecture for application-level resource management. In Proceedings of the Fifteenth ACM Symposium on Operating Systems Principles, SOSP 95, 1995.
10. G. Giannopoulou, N. Stoimenov, P. Huang, L. Thiele, and B. D. de Dinechin. Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. Real-Time Systems, May 2015.
11. Infineon. AURIX-TC27xB-Step, 32-bit Single Chip Micro-controller, Users Manual, vl4.1, February, 2014.
12. P. Kutch. PCISIG SR-IOV Primer-An Introduction to SRIOV Technology. Technical report, Intel Cooperation, January 2011. URL http://www. intel.com/content/www/us/en/pci-\\express/pci-sig-sr-iov-primer-sr-iov-Technology-\ \paper.html.
13. J. Nowotsch and M. Paulitsch. Leveraging multi-core computing architectures in avionics. In Dependable Computing Conference (EDCC), 2012 Ninth European, pages 132-143, May 2012. .
14. S. of Automotive Engineers (SAE). Arp 4754: (aerospace recommended practice)-certification considerations for highly integrated or complex aircraft systems, 2010.
15. J. Reineke, D. Grund, C. Berg, and R. Wilhelm. Timing predictability of cache replacement policies. Real-Time Systems, 37(2):99-122, nov 2007.
16. R.Kaiser. The pikeos concept history and design, sysgo, white paper, 2007.
17. RTCA. do-178b/ed-12b-software considerations in air-borne systems and equipment certification". Technical report, RTCA, Inc, 1st December 1992.
18. RTCA. "do-254/ed-80-design assurance guidance for airborne electronic hardware". Technical report, RTCA, Inc, 19th April 2000.
19. K. Sandstrom, A. Vulgarakis, M. Lindgren, and T. Nolte. Virtualization technologies in embedded real-Time systems. In Emerging Technologies Factory Automation (ETFA), 2013 IEEE 18th Conference on, pages 1-8, Sept 2013. .
20. S. Trujillo, A. Crespo, A. Alonso, and J. Ṕerez. Multipartes: Multicore partitioning and virtualization for easing the certification of mixed-criticality systems. Microprocessors and Microsystems-Embedded Hardware Design, 38(8):921-932, 2014. . URL http: //dx.doi.org/10.1016/j.micpro.2014.09.004.
21. T. Ungerer, C. Bradatsch, M. Gerdes, F. Kluge, R. Jahr, J. Mische, J. Fernandes, P. G. Zaykov, Z. Petrov, B. Bddeker, S. Kehr, H. Regler, A. Hugl, C. Rochange, H. Ozaktas, H. Cass, A. Bonenfant, P. Sainrat, I. Broster, N. Lay, D. George, E. Quiones, M. Panic, J. Abella, F. Cazorla, S. Uhrig, M. Rohde, and A. Pyka. parmerasa-multicore execution of parallelised hard real-Time applications supporting analysability. In Proceedings of the 2013 Euromicro Conference on Digital System Design, DSD 13, pages 363-370. IEEE Computer Society, 2013. ISBN 978-1-4799-2978-8. . URL http://dx.doi. org/10.1109/DSD.2013.46.
22. C. Watkins and R. Walter. Transitioning from federated avionics architectures to integrated modular avionics. In Digital Avionics Systems Conference, 2007. DASC 07. IEEE/AIAA 26th, pages 2.A.1-1-2.A.1-10, Oct 2007. .
23. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transaction on Computer-Aided Design, 28(7):966-978, july 2009.
24. H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proc. of the IEEE, 83(10):1374-1396, 1995.