A 7 level metallization with Cu damascene process using newly developed abrasive free polishing

Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Volumn , Issue , 2000, Pages 264-266

  Yamaguchi, H ^a   Ohashi, N ^a   Imai, T ^a   Torii, K ^a   Noguchi, J ^a   Fujiwara, T ^a   Saito, T ^a   Owada, N ^a   Homma, Y ^a   Kondo, S ^a   Hinode, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ABRASIVES; CACHE MEMORY; CAPACITANCE; CORROSION RESISTANCE; DEFECT DENSITY; METALLIZING; METALS; POLISHING; STATIC RANDOM ACCESS STORAGE;

ABRASIVE-FREE POLISHING; CU DAMASCENE; CU METALLIZATION; DAMASCENE TECHNIQUE; DIELECTRIC LAYER; METALLIZATION STRUCTURES; PARASITIC CAPACITANCE; TDDB LIFETIME;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84962861311     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2000.854343     Document Type: Conference Paper

References (5)

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