Comparing and contrasting a commercial OLTP workload with CPU2000 on IPF

2002 IEEE International Workshop on Workload Characterization, WWC 2002

Volumn , Issue , 2002, Pages 49-58

  Rupley, J ^a   Annavaram, M ^a   De Vale, J ^a   Diep, T ^a   Black, B ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROGRAM PROCESSORS;

ENTERPRISE SERVERS; INSTRUCTION CACHE MISS; ITANIUM PROCESSOR FAMILY; MEMORY FOOTPRINT; MEMORY OPERATIONS; ONLINE TRANSACTION PROCESSING; ORACLE DATABASE; REGISTER STACK ENGINES;

CACHE MEMORY;

EID: 84962853084     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WWC.2002.1226493     Document Type: Conference Paper

References (23)

1. A. Ailamaki, D. DeWitt, M. Hill, and D. Wood, "DBMSs on a Modern Processor: Where Does Time Go?", In Proceedings of the 25th International Conference on Very Large Data Bases, pages 266-277, September 1999.
2. M. Annavaram, T. Diep, and J. Shen, "Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors", In Proceedings of the International Conference on Computer Design, pages 242-248, September 2002.
3. M. Annavaram, J. Patel, E. Davidson, "Call Graph Prefetching for Database Applications", In Proceedings of the 7th Annual International Symposium on High Performance Computer Architecture, pages 281-290, January 2001.
4. B. Calder, G. Reinmann, D. Tullsen, "Selective Value Prediction", In Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 64-74, May 1999.
5. Y. Choi, A. Knies, L. Gerke, and T. Ngai, "The Impact of If-Conversion and Branch Prediction on Program Execution on the Intel Itanium Processor", In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages. 182-191, December 2001.
6. Z. Cvetanovic and D. Bhandarkar, "Characterization of Alpha-Axp Performance using TP and SPEC Workloads", In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 60-70, April 1994.
7. K. Driesen and U. Holzle, "The Cascaded Predictor: Economical and Adaptive Branch Target Prediction", In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 167-178, June 1998.
8. M. Franklin, W. Alexander, R. Jauhari, A. Maynard, B. Olszewski, "Commercial Workload Performance in the IBM Power2 RISC System/6000 processor", In IBM Journal of Research and Development Vol. 38 No. 5, pages 555-561, 1994.
9. Intel Corporation. Intel Itanium Architecture Software Developer's Manual. Available from http://developer.intel.com/design/Itanium2/manuals/.
10. D. Jimenez and C. Lin, "Dynamic Branch Prediction with Perceptrons", In Proceedings of the 7th Annual International Symposium on High Performance Computer Architecture, pages 197-206, January 2001.
11. K. Keeton, D. Patterson, Y. He, R. Raphael, and W. Baker, "Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads", In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 15-26, June 1998.
12. M. Lipasti, C. Wilkerson, and J. Shen, "Value Locality and Load Value Prediction", In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 138-147, October 1996.
13. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner, "Simics: A Full System Simulation Platform", In Computer Vol: 35 Issue: 2, pages 50-58, February 2002.
14. A. Maynard, C. Donnelly, B. Olszewski, "Contrasting Characteristics and Cache Performance of Technical and Multi-user Commercial Workloads", In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 145-156, October 1994.
15. J. McCormick and A. Knies, "A Brief Analysis of the SPEC CPU2000 Benchmarks on the Intel Itanium2 Processor", HotChips 14, August 2002.
16. S. McFarling, "Combining Branch Predictors", WRL Technical Note TN-36, Digital Equipment Corporation, June 1993.
17. M. Rosenblum, E. Bugnion, S. Herrod, E. Witchel, and A. Gupta, "The Impact of Architectural Trends on Operating System Performance", In Proceedings of the 15th ACM Symposium on Operating Systems Principles, pages 285-298, December 1995.
18. D. Soltis, M. Gibson, and C. McNairy, Itanium2 Processor Microarchitecture Overview", HotChips 14, August 2002.
19. SPEC, "SPEC CPU2000", http://www.spec.org/osg/cpu2000/, January 2000.
20. M. Serrano and Y. Wu, "Memory Performance Analysis of SPEC2000C for the Intel Itanium Processor", In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization, December 2001.
21. J. Smith, "A study of branch prediction strategies", In Proceedings of the 8th Annual International Symposium on Computer Architecture, pages 135-148, May 1981.
22. K. Wang and M. Franklin, "Highly Accurate Data Value Prediction using Hybrid Predictors", In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages. 281-290, December 1997.
23. T. Yeh and Y. Patt, "Alternative implementations of two-level adaptive branch prediction", In Proceedings of the 19th Annual International Symposium on Computer Architecture, pages 124-134, May 1992.