A dual edge transition based BIST approach for passive analog circuits

2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000

Volumn , Issue , 2000, Pages 179-181

  Walker, A ^a   Lala, P K ^b  

^a University of Tennessee   (United States)

^b University of South Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; ANALOG TO DIGITAL CONVERSION; DIGITAL TO ANALOG CONVERSION; MIXED SIGNAL INTEGRATED CIRCUITS; RECONFIGURABLE HARDWARE;

ANALOG BLOCKS; ANALOG TO DIGITAL CONVERTERS; PRIMARY OUTPUTS; PULSE RESPONSE; PULSE STREAM; SECOND ORDERS; TEST SIGNAL GENERATORS; VOLTAGE TRANSITION;

BUILT-IN SELF TEST;

EID: 84961999823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2000.836469     Document Type: Conference Paper

References (7)

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2. Karim Arabi, and Bozena Kaminska,"Design for Testability of Embedded Integrated Operational Amplifiers," IEEE Journal of Solid-State Circuits, vol. 33, no. 4, pp. 573-581, April 1998.
3. M.F. Toner and G.W. Roberts,"A BIST Scheme for an SNR Test of a Sigma-Delta ADC,"International Test Conf., pp. 805-814, 1993.
4. A. Chatterjee and Naveena Nagi,"Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial,"Tenth International Conference on VLSI Design, pp. 388-392, January 1997.
5. Kai Hwang and Faye A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill 1984.
6. M.F. Toner and G.W. Roberts,"A BIST Scheme for SNR, Gain Tracking, and Frequency Response Test of a Sigma-Delta ADC,"IEEE Trans. on Circuits and Systems-II: Analog and Digital Processing, vol. 42, No. 1, January 1995.
7. John P. Uyemura, Circuit Design for CMOS VLSI, Kluwer Academic Publisher 1992.