Jitter in a wireless clock distribution system

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 154-156

  Dickson, T ^a   Floyd, B ^a   O, K ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; ELECTRIC CLOCKS; JITTER; LOCKS (FASTENERS); RECONFIGURABLE HARDWARE; SIGNAL RECEIVERS;

CLOCK DISTRIBUTION SYSTEM; CLOCK-JITTER; DISTRIBUTED CLOCKS; EXTREME CONDITIONS; RECEIVER CIRCUITS; RECEIVER SENSITIVITY; SELF-OSCILLATION FREQUENCY; TRANSMITTED POWER;

LOW NOISE AMPLIFIERS;

EID: 84961695926     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014917     Document Type: Conference Paper

References (11)

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3. B.A. Floyd, C.-M. Hung, and K.K. O, Symposium of VLSI Circuit Digest of Technical Papers, June, 2001.
4. A. Deutsch, et al, IEDM Technical Digest, pp. 295-298, Dec. 1998.
5. J. Mehta, and K. K. O, Accepted to IEEE Trans. on Electro-Magnetic Compatibility.
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7. B.A. Floyd, K. Kim, and K.K. O, ISSCC Dig. Tech. Papers, Feb., 2000, pp. 328-329.
8. N.K. Verghese and D. Allstot, IEEE J. Solid-State Circuits, Mar., 1998, pp. 314-323.
9. N.A. Kurd et al, IEEE J. Solid-State Circuits, Nov, 2001, pp. 1647-1653.
10. B. A. Floyd, Ph.D. Dissertation, U. of Florida, 2001.
11. A.J. van Genderen, N.P. van der Meijs, and T. Smedes, Technical Report, ET-CAS 96-03, Delft University of Technology, Dept. of EE, Delft, The Netherlands, August 1996.