Fabrication of 60-nm plasma doped CMOS transistors

Proceedings of the International Conference on Ion Implantation Technology

Volumn 22-27-September-2002, Issue , 2002, Pages 36-39

  Lenoble, D ^a   Grouillet, A ^a   Boeuf, F ^a   Skotnicki, T ^a   Hacker, D ^b   Scheuer, J ^b   Walther, S ^b  

^a STMICROELECTRONICS   (France)

^b Varian SEA   (United States)

Author keywords

60nm CMOS; AsH3 and BF3 plasma doping; ion implantation

Indexed keywords

ION IMPLANTATION; SEMICONDUCTOR DOPING;

BORON TRIFLUORIDE; DEVICE PERFORMANCE; PLASMA DOPING; PLASMA DOPING PROCESS; PULSED PLASMA DOPING; SHORT-CHANNEL EFFECT; SOURCE-DRAIN EXTENSIONS; ULTRA SHALLOW JUNCTION;

IONS;

EID: 84961357942     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIT.2002.1257932     Document Type: Conference Paper

References (4)

1. T. Skotnicki, ESSDERC2000, pp 19-31 (Leuven)
2. D. Lenoble, et al., "Direct comparison of electrical performance of 0.1μm pMOSFETs doped by plasma doping or low energy ion implantation", Ion Implant Technology 2000, pp. 468-471
3. D. Lenoble, P. Prod'homme, D. Beutier, C. Julien, « Evaluation of the impact of energy contamination of ultra-low energy implants on sub-0.1μm CMOS device performance », these proceedings
4. D. Lenoble, et al., VLSI technology symposium, 2000