Formal verification of explicitly parallel microprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 23-26

  Cook, Byron ^a   Launchbury, John ^a   Matthews, John ^a   Kieburtz, Dick ^a  

^a OREGON HEALTH AND SCIENCE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; FORMAL VERIFICATION; HARDWARE; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

ARCHITECTURAL MODELING; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SET ARCHITECTURE; INSTRUCTION SET EXTENSION; MICROPROCESSOR DESIGNS; MULTIMEDIA INSTRUCTION; PARALLEL INSTRUCTIONS; SPECIFICATION AND VERIFICATION;

COMPUTER ARCHITECTURE;

EID: 84958674006     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_4     Document Type: Conference Paper

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