메뉴 건너뛰기




Volumn 1166, Issue , 1996, Pages 435-449

BDDs vs. Zero-suppressed Bdds: For CTL symbolic model checking of Petri nets

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; PETRI NETS;

EID: 84957708535     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0031826     Document Type: Conference Paper
Times cited : (30)

References (10)
  • 6
    • 84947925823 scopus 로고
    • Trace theoretic verification of asynchronous circuits using unfoldings
    • K.L. McMillan. Trace theoretic verification of asynchronous circuits using unfoldings. LNCS 939 Computer aided verification, pages 180-195, 1995.
    • (1995) LNCS 939 Computer Aided Verification , pp. 180-195
    • McMillan, K.L.1
  • 7
    • 0027211369 scopus 로고
    • Zero-suppressed BDDs for set manipulation in combinatorial problems
    • Shinichi Minato. Zero-suppressed BDDs for set manipulation in combinatorial problems. Proc. of 30th DAC, pages 272-277, 1993.
    • (1993) Proc. Of 30Th DAC , pp. 272-277
    • Minato, S.1
  • 8
    • 84956869194 scopus 로고
    • Verification of asynchronous circuits by BDD-based model checking of Petri nets
    • Oriol Roig, Jordi Cortadella, and Enric Pastor. Verification of asynchronous circuits by BDD-based model checking of Petri nets. LNCS 935 Application and theory of Petri nets 1995, pages 374-391, 1995.
    • (1995) LNCS 935 Application and Theory of Petri Nets , vol.1995 , pp. 374-391
    • Roig, O.1    Cortadella, J.2    Pastor, E.3
  • 9
    • 0029482463 scopus 로고
    • Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits
    • Alexei Semenov and Alexandre Yakovlev. Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits. Proc. of CHDL’95, pages 567-573, 1995.
    • (1995) Proc. Of CHDL’95 , pp. 567-573
    • Semenov, A.1    Yakovlev, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.