Automatic verification of combinational and pipelined FFT circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1633, Issue , 1999, Pages 380-393

  Bjesse, Per ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED ANALYSIS; FAST FOURIER TRANSFORMS; TIMING CIRCUITS;

AUTOMATIC COMBINATION; AUTOMATIC VERIFICATION; COMPLEX DATA; EQUIVALENCE CHECKING; FFT CIRCUITS; HARDWARE COMPONENTS; PIPELINED CIRCUITS; PROOF STRATEGY;

PIPELINES;

EID: 84957077865     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48683-6_33     Document Type: Conference Paper

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