Automatic identification of swappable logic units in XC6200 circuitry

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1304, Issue , 1997, Pages 173-182

  Brebner, Gordon ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84956856012     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_222     Document Type: Conference Paper

References (7)

1. Brebner, “A Virtual Hardware Operating System for the Xilinx XC62Q0”, Proc. 6th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 1142, 1996, pp.327-336.
2. Brebner, “CHASTE: a Hardware-Software Co-design Testbed for the Xilinx XC6200”, Proc. 4th Reconfigurable Architecture Workshop, ITpress Verlag, 1997, pp.16-23.
3. Brebner, “The Swappable Logic Unit: a Paradigm for Virtual Hardware”, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.
4. Burns, Donlin, Hogg, Singh and Watt “A Dynamic Reconfiguration Run Time System”, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.
5. Kean, Churcher and Wilkie,: “XC6200 Fastmap Processor Interface,” Proc. 5th International Workshop on Field Programmable Logic and Applications, Springer LNCS 975, 1995, pp.36-43.
6. Luk, Shirazi and Cheung, “Compilation Tools for Run-Time Reconfigurable Designs”, Proc. 5th Annual IEEE Symposium on Custom Computing Machines, IEEE Computer Society Press 1997.
7. Xilinx Inc., XC6200 advance product specification, Xilinx 1996.