The effect of using state-based priority information in a shared-memory multiprocessor cache replacement policy

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 1998, Pages 217-224

  Mounes Toussi, Farnaz ^a   Lilja, David J ^b  

^a IBM   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS;

ACCESS PATTERNS; ASSOCIATIVITY; CACHE BLOCKS; CACHE REPLACEMENT POLICY; COHERENCE STATE; PRIORITY ASSIGNMENT; RANDOM REPLACEMENTS; SHARED MEMORY MULTIPROCESSOR;

CACHE MEMORY;

EID: 19744368384     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1998.708489     Document Type: Conference Paper

References (9)

1. D. H. Bailey, E. Barszcz, J. T. Barton, D. S. Browning, R. L. Carter, L. Dagum, R. A. Fatoohi, P. O. Frederickson, T. A. Lasinski, R. S. Schreiber, H. D. Simon, V. Venkatakrishnan, and S. K. Weeratunga. The NAS Parallel Benchmarks. International Journal of Supercomputer Applications, 5(3):63-73, 1991.
2. Y. Deville. A low-cost-based replacement algorithm for cache memories. Computer Architecture News, pages 52-58, 1990.
3. E. D. Granston and A. V. Veidenbaum. An integrated hardware/software solution for effective management of local storage in high-performance systems. International Conference on Parallel Processing, pages 83-90, 1991.
4. R. H. Katz, S. Eggers, D. Wood, C. L. Perkins, and R. Sheldon. Implementing a cache consistency protocol. International Symposium on Computer Architecture, pages 276-283, 1985.
5. F. Mounes-Toussi, K. Imming, D. Krolak, and D. J. Lilja. The implementation impact of state-based priority information in a shared-memory cache replacement policy. Technical Report HPPC-98-05, University of Minnesota, May 1998. High-Performance Parallel Computing Research Group.
6. A. J. Smith. Cache memories. ACM Computing Surveys, 14:473-530, September 1982.
7. K. So and R. N. Rechtschaffen. Cache operations by MRU change. IEEE Transactions on Computers, 37(6):700-707, June 1988.
8. J. E. Veenstra and R. J. Fowler. MINT tutorial and user manual. Technical Report 452, University of Rochester, June 1993. Department of Computer Science.
9. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH2 programs: Characterization and methodological considerations. International Symposium on Computer Architecture, pages 24-36, June 1995.