Fast analytical thermal modeling of electronic devices and circuits with multi-layer stack mountings

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 501-506

  Bagnoli, P E ^a   Montesi, M ^a   Casarosa, C ^a   Pasquinelli, G ^b  

^a UNIVERSITY OF PISA   (Italy)

^b Lab Materials and Structures Mechanics ISTI A Faedo   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT; ELECTRONICS PACKAGING; HEAT FLUX; MAPPING; THERMOELECTRIC EQUIPMENT;

AUTOMATIC DESIGN TOOLS; DEGREE OF ASYMMETRY; ELECTRONIC DEVICE; HOMOGENEOUS LAYERS; MULTILAYER STACKS; STEADY-STATE TEMPERATURE; THERMAL SIMULATIONS; THERMAL SIMULATORS;

FINITE ELEMENT METHOD;

EID: 84954048003     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271572     Document Type: Conference Paper

References (7)

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3. Bagnoli, P. E. et al, "Study of hot-spot phenomena in cellular power transistors by analytical electro-thermal simulation", Proc. of ESSDERC 02, Florence, Italy 2002.
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