Efficient νMOS realization of threshold voters for self-purging redundancy

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 321-326

  Quintana, J M ^a   Avedillo, M J ^a   Rodriguez Villegas E ^a   Rueda, A ^a  

^a Centro Informatico Cientifico de Andalucia   (Spain)

Author keywords

Circuits; Clocks; Fault tolerance; Hardware; Redundancy; Switches; Tin; Voting

Indexed keywords

CLOCKS; COMPUTER HARDWARE; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); REDUNDANCY; SWITCHES; SYSTEMS ANALYSIS; TIN;

AUTOMATIC THRESHOLD; CIRCUIT REALIZATION; EFFICIENT DECOMPOSITION; HYBRID TECHNIQUES; MULTIPLE FAILURES; REDUNDANCY SCHEME; SWITCHING MECHANISM; VOTING;

FAULT TOLERANCE;

EID: 84951863722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876049     Document Type: Conference Paper

References (11)

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