Direct mapped cache performance modeling for sparse matrix operations

Proceedings of the 7th Euromicro Workshop on Parallel and Distributed Processing, PDP 1999

Volumn , Issue , 1999, Pages 331-338

  Doallo, Ramón ^a   Fraguela, Basilio B ^a   Zapata, Emilio L ^b  

^a UNIVERSITY OF A CORUÑA   (Spain)

^b UNIVERSITY OF MÁLAGA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MATRIX ALGEBRA; PROBABILITY DISTRIBUTIONS;

ACCESS PATTERNS; CACHE PERFORMANCE; DIRECT MAPPED CACHE; MATRIX OPERATIONS; MEMORY SAVINGS; NUMERICAL APPLICATIONS; PERFORMANCE MODELING; PROBABILISTIC MODELS; SPARSE MATRICES;

MEMORY ARCHITECTURE;

EID: 84951134599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMPDP.1999.746696     Document Type: Conference Paper

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