Cache-In-Memory

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2001-January, Issue , 2000, Pages 3-11

  Zawodny, J T ^a   Kogge, P M ^a  

^a University of Notre Dame   (United States)

Author keywords

DRAM chips

Indexed keywords

COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS;

CLASSICAL TECHNIQUES; DRAM CHIPS; HIGH BANDWIDTH; LOW LATENCY; MEMORY MACRO; PERFORMANCE GAIN; POWER SAVINGS; PROCESSING IN MEMORY;

CACHE MEMORY;

EID: 84951032140     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2001.955191     Document Type: Conference Paper

References (14)

1. Jay B. Brockman, Peter, M. Kogge, Vincent Freeh, and Thomas Sterling, "Microservers: A New Memory Semantics for Massively Parallel Computing," Int. Conf. on Supercomputing, Rhodes, Greece, June 20-25, 1999, pp. 454-463.
2. B. Cmelik. The SHADE Simulator, Technical Report, SUN Corp., 1993.
3. Richard Fromm, et al, "The Energy Efficiency of IRAM Architectures," Int. Symp.on Computer Architecture (ISCA), 1997, pp. 327-337.
4. Mary Hall, Peter Kogge, Jeff Koller, Pedro Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss, John Granacki, Apoorv Srivastava, William Athas, Jay Brockman, Vincent Freeh, Joonseok Park, Jaewook Shin, "Mapping Irregular Applications to DIVA, A PIM-based Data-Intensive Architecture," Supercomputing, Portland, OR, Nov. 1999.
5. IBM Microelectronics, "IBM chip advances spur "system-on-a-chip" products," www.chips.ibm.com/news/1999/sa27e/, Feb. 22, 1999.
6. Peter M. Kogge, S. C. Bass, J. B. Brockman, D. Z. Chen, E, H. Sha, "Pursuing a Petaflop: Point designs for 100TF Computers Using PIM Technologies," 6th Symp. on Frontiers of Massively Parallel Computation, Annapolis, MD, Oct. 25-31, 1996
7. Peter M. Kogge, Jay B. Brockman, Thomas Sterling, and Guang Gao, "Processing-In-Memory: Chips to Petaflops," IRAM Workshop, Int. Symp. on Computer Arch., Denver, CO, June 1, 1997.
8. Peter M. Kogge, Jay B. Brockman, Vincent Freeh "Processing-In-Memory Based Systems: Performance Evaluation Considerations", Workshop on Performance Analysis and its Impact on Design, held in conjunction with Int. Symp.on Computer Architecture (ISCA) '98, June 27-28, 1998.
9. Peter M. Kogge, Vincent W. Freeh, Kanad Ghose, Nikzad Toomarian, Nazeeh Aranti, "Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
10. Kartik Nanda, Analysis and Optimization of PIM Memory Organization, M. S. Thesis, Dept. of Computer Science and Engineering, Univ. of Notre Dame, Notre Dame, IN, July 1998.
11. D. Patterson et al., "A Case for Intelligent DRAM: IRAM," IEEE Micro, April 1997.
12. Semiconductor Industry Association, International Technology Roadmap for Semiconductors - 1998 Update, http://notes.sematech.org/ntrs/Rdmpmem.nsf.
13. Jason T. Zawodny and Peter M. Kogge, "Cache-In-Memory: A Lower Power Alternative," Workshop on Power-Driven Microarchitecture, Int. Symp.on Computer Architecture (ISCA), Barcelona, Spain, June 27-28, 1998.
14. Jason T. Zawodny, Cache-In-Memory: Searching for Lower Energy Embedded DRAM, M. S. Thesis, Dept. of Computer Science and Engineering, Univ. of Notre Dame, Notre Dame, IN, October, 2000.