An efficient algorithm for pointer-to-array access conversion for compiling and optimizing DSP applications

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2001-January, Issue , 2000, Pages 80-89

  Van Engelen, R A ^a   Gallivan, K A ^a  

^a Florida State University   (United States)

Author keywords

Optimizing compilers

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; HARDWARE; HIGH LEVEL LANGUAGES; OPTIMIZATION; PROGRAM COMPILERS; SIGNAL PROCESSING; SOFTWARE DESIGN;

DIGITAL SIGNAL PROCESSING (DSP) APPLICATIONS; EMBEDDED PROCESSORS; HARDWARE RESOURCES; HIGH-LEVEL PROGRAMMING LANGUAGE; LOOP OPTIMIZATIONS; OPTIMIZING COMPILERS; POINTER ARITHMETIC; TIMING CONSTRAINTS;

C (PROGRAMMING LANGUAGE);

EID: 84951005762     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2001.955200     Document Type: Conference Paper

References (27)

1. A. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley Publishing Company, Reading MA, 1985.
2. F. Allen, J. Cocke, and K. Kennedy. Reduction of operator strength. In S. Muchnick and N. Jones, editors, Program Flow Analysis, pages 79-101, New-Jersey, 1981. Prentice-Hall.
3. R. Allen and S. Johnson. Compiling C for vectorization, parallelization, and inline expansion. In Proc. of the SIGPLAN 1988 Conference of Programming Languages Design and Implementation, pages 241-249, Atlanta, GA, June 1988.
4. Z. Ammerguallat and W. Harrison III. Automatic recognition of induction variables and recurrence relations by abstract interpretation. In Proc. of the ACM SIGPLAN'90 Conf. on Programming Language Design and Implementation, pages 283-295, White Plains, NY, 1990.
5. O. Bachmann. Chains of Recurrences. PhD thesis, Kent State University of Arts and Sciences, 1996.
6. O. Bachmann, P. Wang, and E. Zima. Chains of recurrences - a method to expedite the evaluation of closed-form functions. In International Symposium on Symbolic and Algebraic Computing, pages 242-249, Oxford, 1994. ACM.
7. A. Basu, R. Leupers, and P. Marwedel. Array index allocation under register constraints in DSP programs. In 12th Int. Conf. on VLSI Design, Goa, India, 1999.
8. M. Cintra and G. Araujo. Array reference allocation using SSA-form and live range growth. In Proc. of the ACM SIGPLAN 2000 LCTES, pages 26-33, Vancouver, June 2000.
9. E. Duesterwald, R. Gupta, and M. Soffa. A practical data flow framework for array reference analysis and its use in optimizations. In Proc. of the SIGPLAN Conference on Programming Languages Design and Implementation, pages 67-77, Albuquerque, New Mexico, 1993.
10. R. Eigenmann, J. Hoeflinger, G. Jaxon, Z. Li, and D. Padua. Restructuring Fortran programs for Cedar. In Proc. of ICPP'91, volume 1, pages 57-66, St. Charles, Illinois, 1991.
11. th Annual Workshop on Languages and Compilers for Parallel Computing, LNCS 589, pages 65-83, Santa Clara, CA, 1991. Springer Verlag.
12. European Telecommunication Standard (ETSI). Digital cellular telecommunications system: ANSI-C code for the GSM enhanced full rate (EFR) speech codec. Available from http://www.etsi.org.
13. B. Franke and M. O'Boyle. Compiler transformation of pointers to explicit array accesses in DSP applications. In Proc. of the ETAPS Conf. on Compiler Construction 2001, LNCS 2027, pages 69-85, 2001.
14. M. Gerlek, E. Stolz, and M. Wolfe. Beyond induction variables: Detecting and classifying sequences using a demand-driven ssa form. ACM Transactions on Programming Languages and Systems (TOPLAS), 17(1):85-122, Jan. 1995.
15. th Annual Workshop on Languages and Compilers for Parallel Computing, LNCS 757, pages 538-562, New Haven, Connecticut, 1992. Springer Verlag.
16. M. R. Haghighat. Symbolic Analysis for Parallelizing Compilers. Kluwer Academic Publishers, 1995.
17. nd European DSP Education and Research Conference, Paris, France, 1998.
18. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann, San Fransisco, CA, 1997.
19. J. Singh and J. Hennessy. An emperical investigation of the effectiviness and limitations of automatic parallelization. In N. Suzuki, editor, Shared Memory Multiprocessing, pages 203-207. MIT press, Cambridge MA, 1992.
20. R. van Engelen. Symbolic evaluation of chains of recurrences for loop optimization. Technical report, TR-000102, Computer Science Dept., Florida State University, 2000.
21. R. A. van Engelen. Efficient symbolic analysis for optimizing compilers. In Proc. of the ETAPS Conference on Compiler Construction 2001, LNCS 2027, pages 118-132, 2001.
22. M. Wolfe. Beyond induction variables. In ACM SIGPLAN'92 Conf. on Programming Language Design and Implementation, pages 162-174, San Fransisco, CA, 1992.
23. M. Wolfe. High Performance Compilers for Parallel Computers. Addison-Wesley, Redwood City, CA, 1996.
24. T. Z. Yu, F. Chen, and E. H.-M. Sha. Loop scheduling algorithms for power reduction. In Proc. of the IEEE International Conference on Acoustics, Speech, and Signal Processing, Seattle, Washington, May 1998.
25. E. Zima. Recurrent relations and speed-up of computations using computer algebra systems. In Proc. of DISCO'92, pages 152-161. LNCS 721, 1992.
26. E. Zima. Simplification and optimization transformations of chains of recurrences. In Proc. of the International Symposium on Symbolic and Algebraic Computing, Montreal, Canada, 1995. ACM.
27. H. Zima. Supercompilers for Parallel and Vector Computers. ACM Press, New York, 1990.